VCC-5CL4MHS
Rev.905-0079-01
©2017 CIS Corporation. All rights reserved.
12
7.
Timing Chart
7.1.
Horizontal Synchronous Signals Timing (10Tap8bit Configuration)
Camera Link Port D
Camera Link Port C
LVAL Out
~ ~
Effective Data : 245 CLK
3 CLK
1H = 248 CLK
Camera Link Port B
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
Camera Link Port A
1
3
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
2
4
2441
2443
2442
2444
1
2
Video Out
2
4
4
9
2
4
5
0
3
4
~ ~
2
4
4
7
2
4
4
8
Camera Link Port H
Camera Link Port G
Camera Link Port F
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
Camera Link Port E
5
7
6
8
2445
2447
2446
2448
5
6
7
8
2
4
4
5
2
4
4
6
2
4
4
3
2
4
4
4
Camera Link Port J
Camera Link Port I
9
10
2449(dummy)
2450(dummy)
2
4
4
1
2
4
4
2
9
1
0
Camera Link
CLK : 84.86MHz
7.2.
Vertical Synchronous Signals Timing (10Tap8bit Configuration)
FVAL Out
1Frame = 2094H
Effective Line : 2048H
Effective Line
DVAL Out
~ ~
LVAL Out
~ ~
Effective Line
~ ~
~ ~
V Blanking :46H
Exposure Time
Exposure Out
2
0
4
8
2
0
4
8
1
1
Video Out
~ ~
~ ~
40
H
1H = 2.92us
10Tap8bit Configuration mode: 163.4fps