CS5374
CS5374
19
4.2 Modulator Inputs — INR, INF
The modulator analog inputs are separated into dif-
ferential rough and fine signals (INR±, INF±) to
maximize sampling accuracy. The positive half of
the differential input signal is connected to INR+
and INF+, while the negative half is attached to
INF– and INR–. The INR± pins are switched-ca-
pacitor ‘rough charge’ inputs that pre-charge the
internal analog sampling capacitor before it is con-
nected to the INF± fine input pins.
4.2.1 Modulator Input Impedance
The modulator inputs have a dynamic switched-ca-
pacitor architecture and so have a rough charge in-
put impedance that is inversely proportional to the
input master clock frequency and the input capaci-
tor size, [1 / (f
·
C)].
Internal to the modulator, the rough inputs (INR±)
pre-charge the sampling capacitor used by the fine
inputs (INF±), therefore the input current to the
fine inputs is typically very low and the effective
input impedance is an order of magnitude above
the impedance of the rough inputs.
4.2.2 Modulator Idle Tones — OFST
The modulators are delta-sigma-type and so can
produce “idle tones” in the measurement band-
width when the differential input signal is a steady-
state DC signal near mid-scale. Idle tones result
from low-frequency patterns in the output data
stream and appear in the measurement spectrum as
small tones about -135 dB down from full scale.
By default the OFST bit in the ADCCFG register is
low and idle tones are eliminated within the modu-
lator by adding –60 mV (channel 1) and –35 mV
(channel 2) of internal differential offset during
conversion to push idle tones out of the measure-
ment bandwidth. Care should be taken to ensure
external offset voltages do not negate the internally
added differential offset, or idle tones will reap-
pear.
4.3 Modulator Output — MDATA
The CS5374 modulators are designed to operate
with the CS5376A digital filter. The digital filter
generates the modulator clock and synchronization
signals (MCLK and MSYNC) while receiving
back the modulator one-bit
ΔΣ
conversion data and
over-range flag (MDATA and MFLAG).
4.3.1 Modulator One’s Density
During normal operation the CS5374 modulators
output a
ΔΣ
serial bit stream to the MDATA pin,
with a one’s density proportional to the differential
amplitude of the analog input signal. The output bit
rate from the MDATA output is a divide-by-four of
the input MCLK, and so is nominally 512 kHz.
The MDATA output has a 50% one’s density for a
mid-scale analog input, approximately 86% one’s
density for a positive full-scale analog input, and
approximately 14% one’s density for a negative
full-scale analog input. One’s density of the MDA-
TA output is defined as the ratio of ‘1’ bits to total
bits in the serial bit stream output; i.e. an 86% one’s
density has, on average, a ‘1’ value in 86 of every
100 output data bits.
4.3.2 Decimated 24-bit Output
When the CS5374 modulators operate with the
CS5376A digital filter, the final decimated, 24-bit,
full-scale output code range depends if digital off-
set correction is enabled. With digital offset correc-
tion enabled within the digital filter, amplifier
•
MCLK = 2.048 MHz
•
INR± Internal Input Capacitor = 20 pF
•
Impedance = [1 / (2.048 MHz * 20 pF)] = 24 k
Ω
