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1-5

DS732UM7

Functional Overview of the CS4953xx Chip
CS4953xx Hardware Users Manual

1.2.7 Direct Stream Digital

(DSD) Controller

The CS4953xx also has a DSD controller which allows the DSP to be integrated into a system that supports SACD
audio. The DSD controller pins are shared with the DAI1 and DAI2 ports. The DSD port consists of a bit clock
(DSD_CLK) and six DSD data inputs (DSD[5:0]).

1.2.8 General Purpose I/O

A 32-bit general-purpose I/O (GPIO) port is provided on the CS4953xx chip to enhance system flexibility. Many of
the functional pins can be used for either GPIO or peripherals.

Each GPIO pin can be individually configured as an output, an input, or an input with interrupt. A GPIO interrupt
can be triggered on a rising edge (0-to-1 transition), falling edge (1-to-0 transition), or logic level (either 0 or 1).
Each pin configured as an input with interrupt can be assigned its own interrupt trigger condition. All GPIOs share a
common interrupt vector.

1.2.9 Parallel Control Port (Motorola/Intel Standards)

The CS4953xx parallel control port allows an external device such as a microcontroller to communicate with the
CS4953xx chip using either a Motorola

-type or Intel

-type parallel communication standard. Only one of the two

communication modes can be selected at a time. For external device-control purposes, the CS4953xx is in slave
mode for all communication protocols, although it can request the external device to perform a read. The parallel
control port supports direct memory access (DMA) and can be used simultaneously with the CS4953xx serial
control port.

The parallel control port communication mode selection occurs as the CS4953xx exits a reset condition. The rising
edge of the RESET pin samples the HS[4:0] pins to determine the communication mode and boot style.
Configuration of the three address input pins A[2:0] allows one of the parallel configuration registers to be selected
and accessed.

1.2.10 Serial Control Ports (SPI

™

or I

Standards)

The CS4953xx has two serial control ports (SCP) that support SPI

™

and I

Master/Slave communication modes.

The serial control port allows external devices such as microcontrollers to communicate with the CS4953xx chip

through either I

or SPI

™

serial communication standards and can be configured as either a master or a slave.

The CS4953xx SPI and I

C serial communication modes are identical from a functional standpoint. The main

difference between the two is the protocol being implemented between the CS4953xx and the external device. In

addition, the I

C slave has a true I

C mode that utilizes data flow mechanisms inherent to the I

C protocol. If this

mode is enabled, the I

C slave will hold SCP1_CLK low to delay a transfer as needed.

By default, SCP1 is configured as a slave for external device-controlled data transfers. As a slave, it cannot drive the
clock signal nor initiate data transfers.

By default, SCP2 is configured as a master to access a serial FLASH/EEPROM for either booting the DSP or
retrieving configuration information. As a master, it can drive the clock signal at up to 1/2 of the DSP’s core clock
speed.

The CS4953xx has two additional serial communication pins not specified in either the I

C or SPI specification. The

port uses the SCP1_IRQ pin to indicate that a read message is ready for the host. The port uses the SCP1_BSY pin to
warn the host to pause communication.

A serial control port can be operated simultaneously with the CS4953xx parallel control port.