Cirrus Logic CS4399, Руководство пользователя

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DS1113F1 35
CS4399
4.8 Audio Serial Port (ASP)
• When using XSP or ASP for DoP playback, the serial port sample bit size register (XSP_SPSIZE or ASP_SPSIZE)
must be set per audio content before enabling the XSP or ASP. Note that the XSP_SPSIZE or ASP_SPSIZE must
reflect the length of both DSD marker bits together with audio bits.
4.8.2 Power-Up, Power-Down, and Tristate
The xSP has separate power-down and tristate controls (PDN_xSP and xSP_3ST) for input data paths, which minimizes
power consumption if the input port is not used. xSP master/slave operation is controlled only by the xSP_M/S setting,
irrespective of the PDN_xSP and xSP_3ST settings.
• PDN_xSP. If a serial port’s SDIN functionality is not required, xSP can be powered down by setting PDN_xSP,
which powers down the input data path and clocks of the serial port.
• xSP_3ST. In Master Mode, setting xSP_3ST tri-states the SCLK and LRCK clocks. Before setting an xSP_3ST bit,
the associated serial port must be powered down and must not be powered up until the xSP_3ST bit is cleared. In
Slave Mode, xSP_3ST does not affect the functionality of SCLK and LRCK clocks, given both pins are input pins.
4.8.3 I/O
The ASP port is associated with SDIN1, SCLK1, and LRCK1. The XSP port is associated with SDIN2, SCLK2, and LRCK2,
which are shared with DSD interface:
• SCLKx—Serial data shift clock
• LRCKx—Toggles at external sample rate (Fs
ext
). LRCK (left/right, I²S) identifies each channel’s (left or right)
location in the data word when I²S format is used. LRCK identifies the start of each serialized data word. FSYNC
(frame sync clock, TDM) identifies the start of each TDM frame.
• SDINx—Serial data input
4.8.4 High-Impedance Mode
Serial ports can be placed on a clock bus that allows multiple masters without the need for external buffers. xSP_3ST bits
place the internal buffers for the respective serial-port interface signals in a high-impedance state, allowing another device
to transmit clocks without bus contention. When the CS4399 serial port is a timing slave, its SCLK and LRCK I/Os are
always inputs and are thus unaffected by the xSP_3ST control.
Fig. 4-16 shows the busing for CS4399 master timing
serial-port use case.
Figure 4-16. Serial Port Busing when Master Timed
4.8.5 Clock Generation and Control
The CS4399 has a flexible serial port clock generation subsystem that allows independent clocking of the two serial ports.
When operating as a master port, the serial port provides a bit clock (xSP_SCLK) and a left-right/frame sync signal (xSP_
LRCK/FSYNC).
Note: x = XSP or ASP
Transmitting
Device #1 (DAC)
Transmitting
Device #2
x_SCLK,
x_LRCK
x_3ST
Receiving Device