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DS271PP3

101

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

The bits that must be programmed in the TxCMD
register are described in Table 34.

For each individual packet transmission, the host
must issue a complete Transmit Request. Further-
more, the host must write to the TxCMD register
before each packet transmission, even if the con-
tents of the TxCMD register does not change. The
Transmit Request described above may be in either
Memory Space or I/O Space.

5.7.6 Transmit in Poll Mode

In poll mode, Rdy4TxiE bit (Register B, BufCFG,
Bit 8) must be clear (Interrupt Disabled). The trans-
mit operation occurs in the following order and is
shown in Figure 30.

1) The host bids for frame storage by writing the

Transmit Command to the TxCMD register

(memory base+ 0144h in memory mode and
I/O base + 0004h in I/O mode).

2) The host writes the transmit frame length to the

TxLength register (memory base + 0146h in
memory mode and I/O base + 0006h in I/O
mode). If the transmit length is erroneous, the
command is discarded and the TxBidErr bit
(Register 18, BusST, Bit 7) is set.

3) The host reads the BusST register. This read is

performed in memory mode by reading Regis-
ter 18, at memory base + 0138h. In I/O mode,
the host must first set the PacketPage Pointer at
the correct location by writing 0138h to the
PacketPage Pointer Port (I/O base + 000Ah).
The host can then read the BusST register from
the PacketPage Data Port (I/O base + 000Ch).

4) After reading the register, the Rdy4TxNOW bit

(Bit 8) is checked. If the bit is set, the frame can
be written. If the bit is clear, the host must con-
tinue reading the BusST register (Register 18)
and checking the Rdy4TxNOW bit (Bit 8) until
the bit is set.

When the CS8900A is ready to accept the frame,
the host transfers the entire frame from host mem-
ory to CS8900A memory using “REP” instruction
(REP MOVS starting at memory base + 0A00h in
memory mode, and REP OUT to Receive/Transmit
Data Port (I/O base + 0000h) in I/O mode).

5.7.7 Transmit in Interrupt Mode

In interrupt mode, Rdy4TxiE bit (Register B,
BufCFG, Bit 8) must be set for transmit operation.
Transmit operation occurs in the following order
and is shown in Figure 31.

1) The host bids for frame storage by writing the

Transmit Command to the TxCMD register
(memory base + 0144h in memory mode and
I/O base + 0004h in I/O mode).

2) The host writes the transmit frame length to the

TxLength register (memory base + 0146h in
memory mode and I/O base + 0006h in I/O

Register 9, TxCMD

Bit

Bit Name

Operation

6

7

Tx Start

clear clear

Start preamble after 5 bytes
have been transferred to the
CS8900A.

clear

set

Start preamble after 381
bytes have been trans-
ferred to the CS8900A.

set

clear

Start preamble after 1021
bytes have been trans-
ferred to the CS8900A.

set

set

Start preamble after entire
frame has been transferred
to the CS8900A.

8

Force

When set, the CS8900A dis-
cards any frame data cur-
rently in the transmit buffer.

9

Onecoll

When set, the CS8900A will
not attempt to retransmit
any packet after a collision.

C

InhibitCRC When set, the CS8900A

does not append the 32-bit
CRC value to the end of any
transmit packet.

D

TxPadDis

When set, the CS8900A will
not add pad bits to short
frames.

Table 34. Tx Command Configuration

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Содержание Crystal LAN CS8900A

Страница 1: ...Architecture ISA Personal Computers Its highly integrated design elimi nates the need for costly external components required by other Ethernet controllers The CS8900A includes on chip RAM 10BASE T transmit and receive filters and a direct ISA Bus interface with 24 mA Drivers In addition to high integration the CS8900A offers a broad range of performance features and configuration options Its uniq...

Страница 2: ... Request Signals 18 3 2 4 DMA Signals 18 3 3 Reset and Initialization 19 3 3 1 Reset 19 3 3 1 1 External Reset or ISA Reset 19 3 3 1 2 Power Up Reset 19 3 3 1 3 Power Down Reset 19 3 3 1 4 EEPROM Reset 19 3 3 1 5 Software Initiated Reset 19 3 3 1 6 Hardware HW Standby or Suspend 19 3 3 1 7 Sof tware SW Suspend 19 3 3 2 Allowing Time for Reset Operation 19 3 3 3 Bus Reset Considerations 19 3 3 4 In...

Страница 3: ...Overview 28 3 9 2 Frame Encapsulation and Decapsulation 29 3 9 2 1 Transmission 29 3 9 2 2 Reception 29 3 9 2 3 Enforcing Minimum Frame Size 29 3 9 3 Transmit Error Detection and Handling 30 3 9 3 1 Loss of Carrier 30 3 9 3 2 SQE Error 30 3 9 3 3 Out of Window Late Collision 30 3 9 3 4 Jabber Error 30 3 9 3 5 Transmit Collision 30 3 9 3 6 Transmit Underrun 30 3 9 4 Receive Error Detection and Hand...

Страница 4: ...ransmit Registers 39 4 1 5 Address Filter Registers 39 4 1 6 Receive and Transmit Frame Locations 39 4 2 PacketPage Memory Map 40 4 3 Bus Interface Registers 42 4 3 1 Product Identification Code 42 4 3 2 I O Base Address 42 4 3 3 Interrupt Number 43 4 3 4 DMA Channel Number 43 4 3 5 DMA Start of Frame 44 4 3 6 DMA Frame Count 44 4 3 7 RxDMA Byte Count 44 4 3 8 Memory Base Address 44 4 3 9 Boot PRO...

Страница 5: ...ress IEEE address 72 4 7 Receive and Transmit Frame Locations 73 4 7 1 Receive PacketPage Locations 73 4 7 2 Transmit Locations 73 4 8 Eight and Sixteen Bit Transfers 73 4 8 1 Transferring Odd Byte Aligned Data 74 4 8 2 Random Access to CS8900A Memory 74 4 9 Memory Mode Operation 74 4 9 1 Accesses in Memory Mode 74 4 9 2 Configuring the CS8900A for Memory Mode 74 4 9 3 Basic Memory Mode Transmit 7...

Страница 6: ... Configuring the Destination Address Filter 88 5 3 2 Hash Filter 89 5 3 2 1 Hash Filter Operation 89 5 3 3 Broadcast Frame Hashing Exception 89 5 4 Receive DMA 90 5 4 1 Overview 90 5 4 2 Configuring the CS8900A for DMA Operation 90 5 4 3 DMA Receive Buffer Size 90 5 4 4 Receive DMA Only Operation 91 5 4 5 Committing Buffer Space to a DMAed Frame 92 5 4 6 DMA Buffer Organization 92 5 4 7 RxDMAFrame...

Страница 7: ...106 6 0 1 Loopback Collision Diagnostic Tests 106 6 0 2 Internal Tests 106 6 0 3 External Tests 106 6 0 4 Loopback Tests 106 6 0 5 10BASE T Loopback and Collision Tests 106 6 0 6 AUI Loopback and Collision Tests 106 6 1 Boundary Scan 107 6 1 1 Output Cycle 107 6 1 2 Input Cycle 107 6 1 3 Continuity Cycle 108 7 0 CHARACTERISTICS SPECIFICATIONS 111 7 1 ABSOLUTE MAXIMUM RATINGS 111 7 2 RECOMMENDED OP...

Страница 8: ...collision detection preamble gen eration and detection and CRC generation and test Programmable MAC features include automatic re transmission on collision and automatic padding of transmitted frames 1 1 4 EEPROM Interface The CS8900A provides a simple and efficient seri al EEPROM interface that allows configuration in formation to be stored in an optional EEPROM and then loaded automatically at p...

Страница 9: ... range of configu ration options and performance features allow en gineers to design Ethernet solutions that meet their particular system requirements Adapter card de sign options include A Boot PROM can be added to support diskless applications The 10BASE T transmitter and receiver im pedance can be adjusted to support 100 120 or 150 Ohm twisted pair cables An external Latchable Address bus decod...

Страница 10: ... software to select whichever access method is best suited to each particular CPU ISA bus configuration When compared to older I O space designs PacketPage is faster sim pler and more efficient To boost performance further the CS8900A in cludes several key features that increase throughput and lower CPU overhead including StreamTransfer cuts up to 87 of interrupts to the host CPU during large bloc...

Страница 11: ...2 5 83 80 2 7 15 3 12 1 1 1 1 0 1 µF 1 µF 680 Ω 680 Ω CE OE OE DIR 20 22 19 1 74LS245 XTAL1 XTAL2 SLEEP TEST RES CS DO DI CLK 1 3 2 4 3 5 4 6 93C46 28 62 61 29 7 IRQ10 IRQ11 IRQ12 IRQ5 DRQ5 DACK5 DRQ6 DACK6 DRQ7 DACK7 16 20 SA 0 19 LA 20 23 BALE 4 97 98 93 4 99 kΩ 1 12 V 4 6 20 MHz 0 1 µF 39 2 Ω 1 5 V 4 7 kΩ CS8900A CHIPSEL IOCS16 49 63 75 36 34 64 33 32 30 35 31 15 13 14 16 11 12 99 100 17 39 2 Ω...

Страница 12: ...74 75 25 EEDataOut EESK EECS EEDataIn CHIPSEL DMACK2 DMACK1 DMACK0 DMARQ2 DMARQ1 DMARQ0 SD15 SD14 SD13 SD12 DVDD2 DVSS2 SD11 CSOUT SD10 SD08 SA3 SA4 SA15 SA14 AVSS4 BSTATUS or HC1 TXD TXD AVSS1 AVDD1 RXD RXD AVSS2 AVDD2 TEST SLEEP XTAL1 XTAL2 RES AVSS3 SA0 INTRQ2 INTRQ1 IOCS16 INTRQ0 MEMCS16 SBHE SA1 SA2 INTRQ3 SA9 SA10 SA8 SA11 SA5 SA6 SA7 REFRESH SA19 SA18 SA17 DVDD3 DVSS3 SA16 SD0 AEN IOW IOR I...

Страница 13: ...nput for the Boundary Scan Test AEN should be inactive when performing an IO or memory access and it should be active during a DMA cycle MEMR Memory Read Input PIN 29 Active low input indicates that the host is executing a Memory Read operation MEMW Memory Write Input PIN 28 Active low input indicates that the host is executing a Memory Write operation MEMCS16 Memory Chip Select 16 bit Open Drain ...

Страница 14: ...of an interrupt event Interrupt Request goes low once the Interrupt Status Queue ISQ is read as all 0 s Only one Interrupt Request output is used one is selected during configuration All non selected Interrupt Request outputs are placed in a high impedance state Section 3 2 on page 18 and Section 5 1 on page 79 DMARQ 0 2 DMA Request 3 State PINS 11 13 and 15 Active high 3 Stateable output used by ...

Страница 15: ...tial Output Pair PINS 87 and 88 Differential output pair drives 10 Mb s Manchester encoded data to the 10BASE T transmit pair RXD RXD 10BASE T Receive Differential Input Pair PINS 91 and 92 Differential input pair receives 10 Mb s Manchester encoded data from the 10BASE T receive pair Attachment Unit Interface AUI DO DO AUI Data Out Differential Output Pair PINS 83 and 84 Differential output pair ...

Страница 16: ...etting the HCB1 in the Self Control register LANLED LAN Activity LED Open Drain Output PIN 100 During normal operation this active low output goes low for 6 ms whenever there is a receive packet a transmit packet or a collision During Hardware Standby mode this output is driven low when the receiver detects network activity TEST Test Enable Input Internal Weak Pullup PIN 76 Active low input used t...

Страница 17: ...ond phase of transmission the CS8900A converts the frame into an Ethernet packet then transmits it onto the network The second phase be gins with the CS8900A transmitting the preamble and Start of Frame delimiter as soon as the proper number of bytes has been transferred into its trans mit buffer 5 381 1021 bytes or full frame de pending on configuration The preamble and Start of Frame delimiter a...

Страница 18: ...d for a Write IOW must be low For additional information about I O Mode see Section 4 10 on page 76 3 2 3 Interrupt Request Signals The CS8900A has four interrupt request output pins that can be connected directly to any four of the ISA bus Interrupt Request signals Only one in terrupt output is used at a time It is selected during initialization by writing the interrupt number 0 to 3 into PacketP...

Страница 19: ... 6 is set 3 3 1 6 Hardware HW Standby or Suspend The CS8900A goes though a chip wide reset when ever it enters or exits either HW Standby mode or HW Suspend mode see Section 3 7 on page 26 for more information about HW Standby and Sus pend 3 3 1 7 Sof tware SW Suspend Whenever the CS8900A enters SW Suspend mode all registers and circuits are reset except for the ISA I O Base Address register locat...

Страница 20: ...8900A operates with any of six standard EEPROM s shown in Table 4 PacketPage Address Register Contents Register Descriptions 0020h 0300h I O Base Address 0022h XXXX XXXX XXXX X100 Interrupt Number 0024h XXXX XXXX XXXX XX11 DMA Channel 0026h 0000h DMA Start of Frame Offset 0028h X000h DMA Frame Count 002Ah 0000h DMA Byte Count 002Ch XXX0 0000h Memory Base Address 0030h XXX0 0000h Boot PROM Base Add...

Страница 21: ...oups of configuration data words and a checksum value All of the words in the Reset Configuration Block are read sequential ly by the CS8900A after each reset starting with the header and ending with the checksum Each group of configuration data is used to program a PacketPage register or set of PacketPage registers in some cases with an initial non default value 3 4 3 2 Reset Configuration Block ...

Страница 22: ... Link Byte 20h indicates the number of bytes to be used in this block of configuration data FIRST GROUP of WORDS 01h 2020h Group Header for first group of words Three words to be loaded beginning at 0020h in PacketPage memory 02h 0300h I O Base Address 03h 0003h Interrupt Number 04h 0001h DMA Channel Number SECOND GROUP of WORDS 05h 502Ch Group Header for second group of words Six words to be load...

Страница 23: ...tion Block The EE PROM address of the checksum value can be deter mined by dividing the value stored in the Link Byte by two The checksum value is the 2 s comple ment of the 8 bit sum any carry out of eighth bit is ignored of all the bytes in the Reset Configuration Block excluding the checksum byte This sum in cludes the Reset Configuration Block header at ad dress 00h Since the checksum is calcu...

Страница 24: ...iguration loaded from EEPROM or reset to default configuration the INITD bit is set Register 16 SelfST bit 7 3 5 Programming the EEPROM After initialization the host can access the EE PROM through the CS8900A by writing one of seven commands to the EEPROM Command regis ter PacketPage base 0040h Figure 5 shows the format of the EEPROM Command register 3 5 1 EEPROM Commands The seven commands used t...

Страница 25: ...PROM Operation The CS8900A supports an optional Boot PROM used to store code for remote booting from a net work server 3 6 1 Accessing the Boot PROM To retrieve the data stored in the Boot PROM the host issues a Read command to the Boot PROM as a Memory space access The CS8900A decodes the command and drives the CSOUT pin low causing the data stored in the Boot PROM to be shifted into the bus tran...

Страница 26: ...CS8900A during this time 3 7 1 Hardware Standby Hardware HW Standby is designed for use in sys tems such as portable PC s that may be temporari ly disconnected from the 10BASE T cable It allows the system to conserve power while the LAN is not in use and then automatically restore Ethernet operation once the cable is reconnected In HW Standby mode all analog and digital cir cuitry in the CS8900A i...

Страница 27: ... O space the Write is only used to wake the CS8900A the Write itself is ig nored Upon exit the CS8900A performs a com plete reset and then goes through a normal initialization procedure Any hardware reset takes the chip out of any sleep mode Table 8 summarizes the operation of the three low power modes CS8900A Configuration CS8900A Operation SLEEP Pin 77 HWStandbyE SelfCTL Bit A HWSleepE SelfCTL B...

Страница 28: ...for CS8900A control the HC1E bit Register 15 Self CTL Bit D must be clear When controlled by the host BSTATUS is low whenever the HCB1 bit Register 15 SelfCTL Bit F is set To configure it for host control HC1E must be set Table 10 sum marizes this operation 3 8 1 LED Connection Each LED output is capable of sinking 10 mA to drive an LED directly through a series resistor The output voltage of each...

Страница 29: ... Length and data field is supplied by the host FCS generation by the CS8900A may be disabled by setting the Inhibit CRC bit Register 9 TxCMD bit C Figure 9 shows the Ethernet frame format 3 9 2 2 Reception The MAC receives the incoming packet as a serial stream of NRZ data from the Manchester encod er decoder It begins by checking for the SFD Once the SFD is detected the MAC assumes all subsequent...

Страница 30: ...ision is detected after the first 512 bits have been transmitted the MAC reports a late collision by setting the Out of window bit Register 8 Tx Event Bit 9 The MAC then forces a bad CRC and terminates the transmission If the Out of window iE bit Register 7 TxCFG Bit 9 is set the host is interrupted A late collision may indicate an illegal network configuration 3 9 3 4 Jabber Error If a transmissi...

Страница 31: ...ach station equal access to the network at any given time Any node can attempt to gain access to the network by first completing a deferral process described below af ter the last network activity and then transmitting a packet that will be received by all other stations If two nodes transmit simultaneously a collision oc curs and the colliding packets are corrupted Two primary tasks of the MAC ar...

Страница 32: ...le deferral process 3 9 5 4 Collision Resolution If a collision is detected while the CS8900A is transmitting the MAC responds in one of three ways depending on whether it is a normal collision within the first 512 bits of transmission or a late collision after the first 512 bits of transmission 3 9 5 5 Normal Collisions If a collision is detected before the end of the pre amble and SFD the MAC fi...

Страница 33: ...wait 1 slot time 512 bit times and k is the smaller of n or 10 where n is the number of retransmission attempts 3 9 5 9 Modified Backoff The Modified Backoff is described by the equation 0 r 2k where r a random integer is the number of slot times the MAC must wait and k is 3 for n 3 and k is the smaller of n or 10 for n 3 where n is the number of retransmission attempts The advantage of the Modifi...

Страница 34: ...ceiver or AUI depending on configuration 3 10 2 Carrier Detection The internal Carrier Detection circuit informs the MAC that valid receive data is present by asserting the internal Carrier Sense signal as soon it detects a valid bit pattern 1010b or 0101b for 10BASE T and 1b or 0b for AUI During normal packet recep tion Carrier Sense remains asserted while the frame is being received and is deass...

Страница 35: ...eiver The CS8900A includes an integrated 10BASE T transceiver that is compliant with the relevant por tions of section 14 of the Ethernet standard ISO IEC 8802 3 1993 It includes all analog and digital circuitry needed to interface the CS8900A directly to a simple isolation transformer see Section 7 5 on page 120 for a connection diagram Figure 13 provides a block diagram of the 10BASE T transceiv...

Страница 36: ...termines when valid data is present on the RXD RXD pair In coming signals passing through the receive filter are tested by the squelch circuit Any signal with amplitude less than the squelch threshold either positive or negative depending on polarity is re jected 3 11 3 2 Extended Range The CS8900A supports an Extended Range feature that reduces the 10BASE T receive squelch thresh old by approxima...

Страница 37: ...ed Any data re ceived before the correction of the reversal is ignored 3 11 6 Collision Detection If half duplex operation is selected Register 19 Bit E FDX the CS8900A detects a 10BASE T collision whenever the receiver and transmitter are active simultaneously When a collision is present the Collision Detection circuit informs the MAC by asserting the internal Collision signal see Section 3 9 on ...

Страница 38: ...n circuit is a differential pair re ceiver that detects the presence of collision signals on the CI CI pins The collision signal is generat ed by an external Ethernet transceiver whenever a collision is detected on the Ethernet segment Sec tion 7 3 1 2 of ISO IEC 8802 3 1993 defines the collision signal as a 10 MHz 15 signal with a duty cycle no worse than 60 40 When a collision is present the AUI...

Страница 39: ... Memory space Most of these registers are written only dur ing initialization remaining unchanged while the CS8900A is in normal operating mode The excep tions to this are the DMA registers which are mod ified continually whenever the CS8900A is using DMA These registers are described in more detail in Section 4 3 on page 42 4 1 3 Status and Control Registers The Status and Control registers are t...

Страница 40: ...page 90 002Ch 4 Read Write Memory Base Address Register 20 Bit Section 4 3 on page 42 Section 4 9 on page 74 0030h 4 Read Write Boot PROM Base Address Section 3 6 on page 25 Section 4 3 on page 42 0034h 4 Read Write Boot PROM Address Mask Section 3 6 on page 25 Section 4 3 on page 42 0038h 8 Reserved Note 2 0040h 2 Read Write EEPROM Command Section 3 5 on page 24 Section 4 3 on page 42 0042h 2 Rea...

Страница 41: ...erved Note 2 Frame Location 0400h 2 Read only RXStatus receive status Section 4 7 on page 73 Section 5 2 on page 79 0402h 2 Read only RxLength receive length in bytes Section 4 7 on page 73 Section 5 2 on page 79 0404h Read only Receive Frame Location Section 4 7 on page 73 Section 5 2 on page 79 0A00 Write only Transmit Frame Location Section 4 7 on page 73 Section 5 7 on page 99 PacketPage Addre...

Страница 42: ...e I O Base Address Register describes the base address for the sixteen contiguous locations in the host system s I O space which are used to access the PacketPage registers See Section 4 10 on page 76 The default location is 0300h After reset if no EEPROM is found by the CS8900A then the register has the following initial state If an EEPROM is found then the register s initial value may be set by ...

Страница 43: ...typical application the following bus signals are tied to the following pins See Section 3 2 on page 18 and Section 5 4 on page 90 After reset if no EEPROM is found by the CS8900A then the register has the following initial state which corre sponds to setting all DMRQ pins to high impedance If a EEPROM is found then the register s initial value may be set by the EEPROM See Section 3 3 on page 19 R...

Страница 44: ... 0000 0000 0000 0000 4 3 8 Memory Base Address Read Write Address PacketPage base 002Ch Memory Base Address The lower three bytes 002Ch 002Dh and 002Eh are used for the 20 bit memory base address The upper three nibbles are reserved After reset if no EEPROM is found by the CS8900A then the register has the following initial state If an EEPROM is found then the register s initial value may be set b...

Страница 45: ...the size of the PROM The upper three nibbles are reserved For example See Section 3 6 on page 25 After reset if no EEPROM is found by the CS8900A then the register has the following initial state If an EEPROM is found then the register s initial value may be set by the EEPROM See Section 3 3 on page 19 Reset value is XXXX XXXX XXXX 0000 0000 0000 0000 0000 Address 0033h Address 0032h Address 0031h...

Страница 46: ... 4 3 12 EEPROM Data Read Write Address PacketPage base 0042h This register contains the word being written to or read from the EEPROM See Section 3 5 on page 24 Reset value is XXXX XXXX XXXX XXXX 4 3 13 Receive Frame Byte Counter Read only Address PacketPage base 0050h This register contains the count of the total number bytes received in the the current received frame This count con tinuously inc...

Страница 47: ...ock of Configuration Control Registers and is read only The second location PacketPage base 0144h is where the actual transmit commands are issued and is write only See Section 4 4 4 on page 49 Register 9 and Section 5 7 on page 99 for a more detailed description of the TxCMD register 4 4 2 Status and Event Registers Status and Event registers report the status of trans mitted and received frames ...

Страница 48: ...ounters The Event registers are RxEvent Register 4 Tx Event Register 8 and BufEvent Register C The counters are RxMISS Register 10 and TxCOL Register 12 Each Interrupt Enable bit and its as sociated Event are identified in Table 14 An Event bit will be set whenever the specified event happens whether or not the associated Inter rupt Enable bit is set All Event registers are cleared upon read out b...

Страница 49: ...ge 49 gives a detailed description of each Status and Control register Interrupt Enable Bit register name Event Bit or Counter register name ExtradataiE RxCFG Extradata RxEvent RuntiE RxCFG Runt RxEvent CRCerroriE RxCFG CRCerror RxEvent RxOKiE RxCFG RxOK RxEvent 16colliE TxCFG 16coll TxEvent AnycolliE TxCFG Number of Tx collisions counter is incremented TxEvent JabberiE TxCFG Jabber TxEvent Out of...

Страница 50: ... Loss of CRSiE 7 0106h TxCFG TxPad Dis Inhibit CRC Onecoll Force TxStart 9 0108h TxCMD RxD estiE Miss OvfloiE TxCol OvfloiE Rx128iE Rxmis siE TxUnder runiE Rdy4Txi E RxD MAiE SWint X B 010Ah BufCFG Reserved register contents undefined D 11 LoRx Squelch 2 part DefDis Polarity Dis Mod BackoffE AutoAUI 10BT AUIonly Ser TxON Ser RxON 13 0112h Line CTL HCB1 HCB0 HC1E HC0E HWStan dbyE HW SleepE SW Sus p...

Страница 51: ... Window TxOK SQE error Loss of CRS 8 0128h TxEvent Reserved register contents undefined A Rx Dest Rx128 RxMiss TxUnder run Rdy4Tx RxDMA Frame SWint C 012Ch Buf Event Reserved register contents undefined E 10 bit Receive Miss RxMISS counter cleared when read 10 0130h RxMISS 10 bit Transmit Collision TxCOL counter cleared when read 12 0132h TxCOL CRS Polarity OK 10BT AUI LinkOK 14 0134h LineST EESiz...

Страница 52: ... register to the ISQ register and drives an IRQ pin high Three of the registers mapped to ISQ are event registers RxEvent Register 4 TxEvent Register 8 and BufEvent Register C The other two registers are counter overflow reports RxMISS Register 10 and TxCOL Register 12 In Mem ory Mode ISQ is located at PacketPage base 120h In I O Mode ISQ is located at I O Base 0008h See Section 5 1 on page 79 Reg...

Страница 53: ...y The Receive DMA mode is used for all receive frames when this bit is set AutoRxDMAE When set the CS8900A will automatically switch to Receive DMA mode if the conditions spec ified in Section 5 5 on page 93 are met RxDMAonly Bit 9 has precedence over AutoRxD MAE BufferCRC When set the received CRC is included with the data stored in the receive frame buffer and the four CRC bytes are included in ...

Страница 54: ...ception regarding broadcast frames If Hashed and RxOK are not both set then Bits F through A are individual event bits as defined below IndividualAdr If the received frame had a Destination Address which matched the Individual Address found at PacketPage base 0158h then this bit is set if and only if RxOK Bit 8 is set and Individ ualA Register 5 RxCTL Bit A is set Broadcast If the received frame h...

Страница 55: ...adcastA When set receive frames are accepted if the Destination Address is FFFF FFFF FFFFh CRCerrorA When set receive frames that pass the Destination Address filter but have a bad CRC are ac cepted When clear frames with bad CRC are discarded See Note 5 RuntA When set receive frames that are smaller than 64 bytes and that pass the Destination Address filter are accepted When clear received frames...

Страница 56: ...et an interrupt is generated if a late collision occurs a late collision is a collision which occurs after the first 512 bit times When this occurs the CS8900A forces a bad CRC and ter minates the transmission JabberiE When set an interrupt is generated if a transmission is longer than approximately 26 ms AnycolliE When set if one or more collisions occur during the transmission of a packet an int...

Страница 57: ...s after the first bit of the preamble When this occurs the CS8900A forces a bad CRC and terminates the transmission If Out of window iE Register 7 TxCFG Bit 9 is set there is an interrupt Jabber If the last transmission is longer than 26 msec then the packet output is terminated by the jab ber logic and this bit is set If JabberiE Register 7 TxCFG Bit A is set there is an interrupt of TX collision...

Страница 58: ...transmit command any transmit frames waiting in the trans mit buffer are deleted If a previous packet has started transmission that packet is terminated within 64 bit times with a bad CRC Onecoll When this bit is set any transmission will be terminated after only one collision When clear the CS8900A allows up to 16 normal collisions before terminating the transmission InhibitCRC When set the CRC i...

Страница 59: ...bit Register C BufEvent Bit A is set Rx128iE When set there is an interrupt after the first 128 bytes of a frame have been received This al lows a host processor to examine the Destination Address Source Address Length Sequence Number and other information before the entire frame is received This interrupt should not be used with DMA Thus if either AutoRxDMA Register 3 RxCFG Bit A or RxDMAonly Reg...

Страница 60: ... out of data before it reaches the end of the frame called a trans mit underrun If TxUnderruniE Register B BufCFG Bit 9 is set there is an interrupt RxMiss If set one or more receive frames have been lost due to slow movement of data out of the re ceive buffers If RxMissiE Register B BufCFG Bit A is set there is an interrupt Rx128 This bit is set after the first 128 bytes of an incoming frame have...

Страница 61: ...his interrupt provides the host with an early warning that the RxMISS counter should be read before it reaches 3FFh and starts over by interrupting at 200h the host has an additional 512 counts before RxMISS actually overflows The RxMISS counter is cleared when read 010000 These bits provide an internal address used by the CS8900A to identify this as the Receiver Miss Counter When reading this reg...

Страница 62: ...nts from 1FFh to 200h This interrupt provides the host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over by inter rupting at 200h the host has an additional 512 counts before TxCOL actually overflows The TxCOL counter is cleared when read 010010 These bits provide an internal address used by the CS8900A to identify this as the Transmit Collision Cou...

Страница 63: ...hm is used see Section 3 9 on page 28 When set the Modified Backoff algorithm is used The Modified Backoff algorithm extends the backoff delay after each of the first three Tx collisions PolarityDis The 10BASE T receiver automatically determines the polarity of the received signal at the RXD RXD input see Section 3 11 on page 35 When this bit is clear the polarity is correct ed if necessary When s...

Страница 64: ...ng the AUI 10BT If set the CS8900A is using the 10BASE T interface PolarityOK If set the polarity of the 10BASE T receive signal at the RXD RXD inputs is correct If clear the polarity is reversed If PolarityDis Register 13 LineCTL Bit C is clear the polarity is auto matically corrected if needed The PolarityOK status bit shows the true state of the incoming polarity independent of the PolarityDis ...

Страница 65: ...cription of the CS8900A s low power modes HWStandbyE If HWSleepE is set and the SLEEP input pin is low then when HWStandbyE is set the CS8900A enters the Hardware Standby mode When clear the CS8900A enters the Hardware Suspend mode see Section 3 7 on page 26 for a complete description of the CS8900A s low power modes HC0E The LINKLED or HC0 output pin is selected with this control bit When HC0E is...

Страница 66: ... indicating that the EEPROM is currently being read or pro grammed The host must not write to PacketPage base 0040h nor 0042h until SIBUSY is clear EEPROMpresent If the EEDataIn pin is low after reset there is no EEPROM present and the EEPROMpresent bit is clear If the EEDataIn pin is high after reset the CS8900A assumes that an EEPROM is present and this bit is set EEPROMOK If set the checksum of...

Страница 67: ...e 74 For MEMCS16 pin to be enabled the CS8900A must be in Memory Mode with the MemoryE bit Register 17 BusCTL Bit A set MemoryE When set the CS8900A may operate in Memory Mode When clear Memory Mode is disabled I O Mode is always enabled DMABurst When clear the CS8900A performs continuous DMA until the receive frame is completely transferred from the CS8900A to host memory When set each DMA access...

Страница 68: ...ames that the CS8900A will not send are 1 Any frame greater than 1514 bytes provided that InhibitCRC Register 9 TxCMD Bit C is clear 2 Any frame greater than 1518 bytes Note that this bit is not set when transmit frames are too short Rdy4TxNOW Rdy4TxNOW signals the host that the CS8900A is ready to accept a frame from the host for transmission This bit is similar to Rdy4Tx Register C BufEvent Bit ...

Страница 69: ...connected to the decoder input The 10BASE T and AUI transmitters and receivers are disabled When clear the CS8900A is configured for normal operation AUIloop When set the CS8900A allows reception while transmitting This facilitates loopback tests for the AUI When clear the CS8900A is configured for normal AUI operation Disable Backoff When set the backoff algorithm is disabled The CS8900A transmit...

Страница 70: ...sion on the AUI to when a col lision or Loss of Carrier error occurs The TDR counter is cleared when read 011100 These bits provide an internal address used by the CS8900A to identify this as the Bus Status Register When reading this register these bits will be 011100 where the LSB corresponds to Bit 0 AUI Delay The upper ten bits contains the number of 10 MHz clock periods between the beginning o...

Страница 71: ...a bad CRC Onecoll When this bit is set any transmission will be terminated after only one collision When clear the CS8900A allows up to 16 normal collisions before terminating the transmission InhibitCRC When set the CRC is not appended to the transmission TxPadDis When TxPadDis is clear if the host gives a transmit length less than 60 bytes and InhibitCRC is set then the CS8900A pads to 60 bytes ...

Страница 72: ...ndividual Address IEEE address Read Write Address PacketPage base 0158h The unique IEEE 48 bit Individual Address IA begins at 0158h The first bit of the IA Bit IA 00 must be 0 See Section 5 3 on page 87 The value of this register must be loaded from external storage for example from the EEPROM See Section 3 3 on page 19 If the CS8900A is not able to load the IA from the EEPROM then after a reset ...

Страница 73: ...at CRC has been selected via Register 3 RxCFG bit BufferCRC If CRC has not been selected then the length does not in clude the CRC and the CRC is not present in the receive buffer After the RxLength has been read the receive frame can be read When some portion of the frame is read the entire frame should be read before read ing the RxEvent register either directly or through the ISQ register Readi...

Страница 74: ...A s registers can be accessed di rectly In Memory Mode the CS8900A supports Standard or Ready Bus cycles without introducing additional wait states Memory moves can use MOVD double word transfers as long as the CS8900A s memory base address is on a double word boundary Since 286 processors don t support the MOVD instruction word and byte transfers must be used with a 286 4 9 1 Accesses in Memory M...

Страница 75: ...g the CHIPSEL pin must be tied low the ISA bus SMEMR signal must be connected to the MEMR pin the ISA bus SMEMW signal must be connect ed to the MEMW pin the host must write the memory base address into the Memory Base Address register Pack etPage base 002Ch the host must set the MemoryE bit Register 17 BusCTL Bit A and the host must clear the UseSA bit Register 17 BusCTL Bit 9 4 9 3 Basic Memory ...

Страница 76: ...a Ports 0 and 1 These two ports are used when transferring trans mit data to the CS8900A and receive data from the CS8900A Port 0 is used for 16 bit operations and Ports 0 and 1 are used for 32 bit operations lower order word in Port 0 4 10 2 TxCMD Port The host writes the Transmit Command TxCMD to this port at the start of each transmit operation The Transmit Command tells the CS8900A that the ho...

Страница 77: ...see if the Rdy4TxNOW bit Bit 8 is set To read the BusST register the host must first set the PacketPage Pointer at the correct location by writing 0138h to the PacketPage Pointer Port I O base 000Ah It can then read the BusST register from the PacketPage Data Port I O base 000Ch If Rdy4TxNOW is set the frame can be written If clear the host must wait for CS8900A buffer memory to become available I...

Страница 78: ...ack etPage address of the target register to the PacketPage Pointer Port I O base 000Ah The contents of the target register is then mapped into the PacketPage Data Port I O base 000Ch If the host needs to access a sequential block of reg isters the MSB of the PacketPage address of the first word to be accessed should be set to 1 The PacketPage Pointer will then move to the next word location autom...

Страница 79: ...he corresponding register are cleared and the next report in the queue moves to the front When the host starts reading the ISQ it must read and process all Event reports in the queue A read out of a null word 0000h indicates that all inter rupts have been read The ISQ is read as a 16 bit word The lower six bits 0 through 5 contain the register number 4 8 C 10 or 12 The upper ten bits 6 through F c...

Страница 80: ...ven low No Process applicable RxEvent bits Extradata Runt CRCerror RxOK Process applicable TxEvent bits 16coll Jabber Out of window TxOK Process applicable BufEvent bits RxDest Rx128 RxMiss TxUnderrun Rdy4Tx RxDMAFrame SWint Process RxMISS counter Process TxCOL counter Which Event report type RxEvent TxEvent BufEvent RxMISS TxCOL None of the above Service Default EXIT Interrupts re enabled Interru...

Страница 81: ...e CS8900A s MAC engine The FCS may or may not be transferred depending on the configuration All transfers to and from the CS8900A are counted in bytes but may be padded for double word alignment 5 2 2 Receive Configuration After each reset the CS8900A must be configured for receive operation This can be done automati cally using an attached EEPROM or by writing configuration commands to the CS8900...

Страница 82: ...es that pass the hash filter are accepted A IndividualA When set frames with DA that matches the IA at PacketPage base 0158h are accepted B Broad castA When set all broadcast frames are accepted C CRCerrorA When set frames with bad CRC that pass the DA filter are accepted D RuntA When set frames shorter than 64 bytes that pass the DA filter are accepted E ExtradataA When set frames longer than 151...

Страница 83: ...set DMA slave opera tion used for all receive frames A AutoRX DMAE When set Auto Switch DMA enabled B BufferCRC When set the received CRC is buffered Register 17 BusCTL Bit Bit Name Operation B DMABurst When set DMA operations hold the bus for up to approx imately 28 µs When clear DMA operations are continu ous D RxDMAsize When set DMA buffer size is 64 Kbytes When clear DMA buffer size is 16 Kbyt...

Страница 84: ...cceptance Filtering The third step of pre processing is to determine whether or not to accept the frame by comparing the frame with the criteria programmed into the Rx CTL register Register 5 If the receive frame passes the Acceptance filter the frame is buffered either on chip or in host memory via DMA If the frame fails the Acceptance filter it is discarded The results of the Acceptance filter a...

Страница 85: ...RxOK or CRCerror set as appropriate If RxOKA or CRCerrorA is set frame accepted and Host may read frame Rx128 cleared and RxOK CRCerror or Extradata set as appropriate If ExtradataA RxOKA or CRCerrorA is set frame is accepted and Host may read frame DA Filter Passed Yes No Yes No No Yes Yes No No Yes Rx128 set and RxDest cleared Host may read first 128 received bytes Yes No Discard Frame RxDest se...

Страница 86: ...tPage base 0404h To transfer frames in I O space the host ex ecutes repetitive In instructions REP IN from I O base 0000h with status and length preceding the frame There are three possible ways that the host can learn the status of a particular frame It can 1 Read the Interrupt Status Queue 2 Read the RxEvent register directly Register4 or 3 Read the RxStatus register PacketPage base 0400h 5 2 7 ...

Страница 87: ...mplete frame using the byte count register the register can be read and the data moved until a count of zero is detected Then the RxEvent regis ter can be read to determine the final frame status The sequence is as follows 1 At the start of a frame the byte counter matches the incoming character counter The byte counter will have an even value prior to the end of the frame 2 At the end of the fram...

Страница 88: ... The DA filter is configured by programming five DA filter bits in the RxCTL register Register 5 IAHashA PromiscuousA MulticastA Individua lA and BroadcastA Four of these bits are associat ed with four status bits in the RxEvent register Register 4 IAHash Hashed IndividualAdr and Broadcast The RxEvent register reports the results of the DA filter for a given receive frame The bits associated with ...

Страница 89: ...e base 0150h If the decoder output and the Logical Address Filter bit match the frame passes the hash filter and the Hashed bit Register 4 RxEvent Bit 9 is set If the two do not match the frame fails the filter and the Hashed bit is clear Whenever the hash filter is passed by a good frame the RxOK bit Register 4 RxEvent Bit 8 is set and the bits in the HR are mapped to the Hash Table Index bits Re...

Страница 90: ... receive frames 5 4 3 DMA Receive Buffer Size In receive DMA mode the CS8900A stores re ceived frames along with their status and length in a circular buffer located in host memory space Address Type of Received Frame Erred Frame Passes Hash Filter Contents of RxEvent Bits F A Bit 9 Hashed Bit 8 RxOK Bit 6 IAHash Individual Address no yes Hash Table Index 1 1 1 no no ExtraData Runt CRC Error Broad...

Страница 91: ...it B is clear the DMA Request pin remains high until the entire frame is transferred If the DMABurst bit is set the DMA Request pin DMARQ remains high for approxi mately 28 ms then goes low for approximately 1 3 ms to give the CPU and other peripherals access to the bus When the transfer is complete the CS8900A does the following updates the DMA Start of Frame register PacketPage base 0026h update...

Страница 92: ...start of the most recently transferred received frame Frames stored in the DMA buffer are trans ferred as words and maintain double word 32 bit alignment Unfilled memory space between suc cessive frames stored in the DMA buffer may result from double word alignment These holes may be 1 2 or 3 bytes depending on the length of the frame preceding the hole 5 4 7 RxDMAFrame Bit The RxDMAFrame bit Regi...

Страница 93: ...ffer memory space described by the CDMA counter During the frame processing the software should advance the PDMA_START pointer At the end of processing a frame pointer PDMA_START should be made to align with a double word bound ary The software remains in the loop until the DMA frame count read is zero 5 5 Auto Switch DMA 5 5 1 Overview The CS8900A supports a unique feature Auto Switch DMA that al...

Страница 94: ...ver a frame begins to be received in Auto Switch DMA mode the CS8900A checks to see if there is enough on chip buffer space to store a max imum length frame If there is the incoming frame is pre processed and buffered as normal If there isn t the CS8900A s MAC engine compares the frame s Destination Address DA to the criteria programmed into the DA filter If the incoming DA fails the DA filter the...

Страница 95: ... has been moved to host memory the CS8900A updates the DMA Start of Frame register PacketPage base 0126h the DMA Frame Count register PacketPage base 0128h and the DMA Byte Count register then sets the RxDMAFrame bit Register C BufEvent bit 7 If RxDMAiE Register B BufCFG bit 7 is set a corresponding interrupt occurs 5 5 4 DMA Channel Speed vs Missed Frames When the CS8900A starts DMA the entire ol...

Страница 96: ...t both be set Finally StreamTransfer works on whole packets and is not compatible with early interrupts This requires that the RxDestiE bit and the Rx128iE bit both be clear Table 28 summarizes how to configure the CS8900A for StreamTransfer 5 6 3 StreamTransfer Operation When StreamTransfer is enabled the CS8900A will initiate a StreamTransfer cycle whenever two or more frames with the following ...

Страница 97: ...e host responds to the RxDMAFrame interrupt and reads the Frame Count register which is cleared when read Since there are no receive interrupts pending the CS8900A exits DMA assumes Frame 3 is still coming in Receive DMA used during this time At this point the CS8900A does not have sufficient buffer space for another complete large frame 1518 bytes Frame 1 received and completely stored in on chip...

Страница 98: ... Table 29 summarize the Receive DMA configura tion options supported by the CS8900A 4 Back to Back Frames 5 Back to Back Frames Interrupt Request 9 Interrupts for 9 Good Packets Time T 52 us Figure 28 Receive Example Without Stream Transfer 4 Back to Back Frames 5 Back to Back Frames Interrupt Request 2 Interrupts for 9 Good Packets Time T 52 us Figure 29 Receive DMA Configuration Options RxDMAonl...

Страница 99: ... automati cally using an attached EEPROM or by writing configuration commands to the CS8900A s internal registers see Section 3 4 on page 21 The items that must be configured include which physical in terface to use and which transmit events cause in terrupts 5 7 2 1 Configuring the Physical Interface Configuring the physical interface consists of de termining which Ethernet interface should be ac...

Страница 100: ...n to the TxCMD register tells the CS8900A how to transmit the next frame Register 7 TxCFG Bit Bit Name Operation 6 Loss of CRSiE When set there is an interrupt whenever the CS8900A fails to detect Carrier Sense after trans mitting the preamble applies to the AUI only 7 SQErroriE When set there is an interrupt whenever there is an SQE error 8 TxOKiE When set there is an interrupt whenever a frame i...

Страница 101: ...ecked If the bit is set the frame can be written If the bit is clear the host must con tinue reading the BusST register Register 18 and checking the Rdy4TxNOW bit Bit 8 until the bit is set When the CS8900A is ready to accept the frame the host transfers the entire frame from host mem ory to CS8900A memory using REP instruction REP MOVS starting at memory base 0A00h in memory mode and REP OUT to R...

Страница 102: ...acketPage Pointer at CS8900A Commits Buffer Space to Transmit Frame Host Reads the BusST Register Register 18 Transmit Request Host Writes Transmit Frame to CS8900A Host Writes Transmit Command to the TxCMD Register Host Writes Transmit Frame Length to the TxLength Register Exit Transmit Process Yes No Enter Packet Transmit Process Rdy4 TxNOW bit 1 Polling Loop No Yes Is TxCMD pending Exit can t I...

Страница 103: ...st that space has become available when interrupts are not being used i e the Rdy4TxiE bit Register B BufCFG Bit 8 is not set Also the Rdy4Tx bit is used with interrupts and requires the Rdy4TxiE bit be set Figure 30 provides a diagram of error free trans mission without collision 5 7 10 Committing Buffer Space to a Transmit Frame When the host issues a transmit request the CS8900A checks the leng...

Страница 104: ...r Space to Transmit Frame Host Reads ISQ Host Reads the BusST Register Register 18 Transmit Request Host Writes Transmit Frame to CS8900A Host Writes Transmit Command to the TxCMD Register Host Writes Transmit Frame Length to the TxLength Register Rdy4Tx bit 1 Exit Transmit Process No Yes No Yes Rdy4 TxNOW bit 1 Host Enters Interrupt Routine Exit WAIT for interrupt Process other events that caused...

Страница 105: ... received the count is restarted When auto negotiation occurs a transmitter sends FLPs auto negotiation Fast Link Pulses bursts instead of the original IEEE 802 3 NLP Normal Link Pulses If the hub is attempting to auto negotiate with the CS8900A the CS8900A will never get more than 1 valid link pulse valid NLP This is not a prob lem if the CS8900A is already sending link pulses because when the hu...

Страница 106: ...wo bits in the Test Control register AUIloop Register 19 TestCTL Bit A and ENDECloop Register 19 TestCTL Bit 9 Table 37 describes these tests Test Mode FDX ENDECloop Description of Test 10BASE T Inter nal Loopback 1 1 Transmit a frame and verify that the frame is received without error 10BASE T Inter nal Collision 0 1 Transmit frames and verify that collisions are detected and that the internal co...

Страница 107: ...During the Output Cycle the falling edge of AEN causes each of the 17 digital output pins and each of the 17 bi directional pins to be driven low one at a time The cycle begins with LINKLED and ad vances in order counterclockwise around the chip through all 34 pins This test is referred to as a walking 0 test The following is a list of output pins and bi direc tional pins that are tested during th...

Страница 108: ...Input Cycle and an additional AEN cycle is called a Continuity Cycle Each Continuity Cycle lasts for 85 AEN clock cycles The first Continuity Cycle can be followed by additional Continuity Cycles by keeping TEST low and continuing to cy cle AEN When TEST is driven high the CS8900A exits Boundary Scan mode and AEN is again used as the ISA bus Address Enable Figure 32 shows a complete Boundary Scan ...

Страница 109: ...N switches low Selected output goes low AEN switches high 34 cycles INPUT CYCLE AEN switches low Selected input copied out to the EEDataOut pin AEN switches high 50 cycles All digital output pins and bi directional pins enters High Z state TEST switches low AEN must be low Not in Boundary Scan Test Mode AEN switches low AEN switches high EXIT BOUNDARY SCAN AEN becomes ISA bus Address Enable TEST s...

Страница 110: ...HEET TESTSEL AEN Outputs All outputs tri state LANLED low BSTATUS low EEDataOut RESET copied out ELCS copied out OUTPUTS Hi Z OUTPUT TEST 34 Clocks INPUT TEST 50 Clocks OUTPUTS Hi Z 1 clock COMPLETE CONTINUITY CYCLE 85 Clocks LINKLED low SLEEP copied out Figure 33 Boundary Scan Timing ...

Страница 111: ...ature Power Applied 55 125 C Storage Temperature 65 150 C Parameter Symbol Min Max Unit 5 0V Power Supply CS8900A CQ IQ Digital Analog DVDD AVDD 4 75 4 75 5 25 5 25 V V 3 3V Power Supply CS8900A CQ3 IQ3 Digital Analog DVDD AVDD 3 135 3 135 3 465 3 465 V V Operating Ambient Temperature CS8900A CQ CQ3 TA 0 70 C Operating Ambient Temperature CS8900A IQ IQ3 TA 40 85 C Parameter Symbol Min Max Unit Cry...

Страница 112: ... VOL 0 4 0 4 0 4 V V V Output Low Voltage all outputs VDD 3 3V and TA 70 C VOL 0 425 V Output High Voltage IOH 12 mA B24 IOH 2 mA B4w O24ts O4 VOH 2 4 2 4 V V Output Leakage Current 0 VOUT VCC OD24 OD10 B24 O24ts B4w ILL 10 20 10 10 µA Input Low Voltage I Iw VIL 0 8 V Input High Voltage I Iw VIH 2 4 V Input Leakage Current 0 VIN VCC I Iw IL 10 20 10 10 µA 10BASE T Interface Transmitter Differentia...

Страница 113: ...R inactive tIOR4 0 ns IOR inactive to active tIOR5 35 ns IOR inactive to SD 3 state tIOR6 30 ns 16 Bit I O Read With IOCHRDY IOR active to IORCHRDY inactive tIOR7 30 ns IOCHRDY low pulse width tIOR8 125 175 ns IOCHRDY active to SD valid tIOR9 0 ns SA 15 0 AEN SBHE Valid Address IOCS16 IN DIRECTION IN or OUT of chip IOR SD 15 0 Valid Data OUT IN OUT tIOR1 tIOR2 tIOR3 tIOR4 tIOR5 tIOR6 16 Bit I O Re...

Страница 114: ...ns MEMR inactive to SD 3 state tMEMR5 30 ns MEMR inactive to active tMEMR6 35 ns 16 Bit Memory Read With IOCHRDY MEMR low to IOCHRDY inactive tMEMR7 35 ns IOCHRDY low pulse width tMEMR8 125 175 ns IOCHRDY active to SD valid tMEMR9 0 ns SA 19 0 SBHE CHIPSEL Valid Address MEMCS16 IN DIRECTION IN or OUT of chip MEMR SD 15 0 Valid Data OUT IN OUT tMEMR1 tMEMR2 tMEMR3 tMEMR4 tMEMR5 tMEMR6 16 Bit Memory...

Страница 115: ...16 Bit I O Write Address AEN SBHE valid to IOCS16 low tIOW1 35 ns Address AEN SBHE valid to IOW low tIOW2 20 ns IOW pulse width tIOW3 110 ns SD hold after IOW high tIOW4 0 ns IOW low to SD valid tIOW5 10 ns IOW inactive to active tIOW6 35 ns Address hold after IOW high tIOW7 0 ns DIRECTION IN or OUT of chip SD 15 0 OUT IOR DMARQx OUT IN DMACKx IN AEN IN tDMA1 IORn IORn 1 tDMA2 Valid Data Valid Dat...

Страница 116: ... tMEMW4 40 ns SD hold after MEMW high tMEMW5 0 ns Address hold after MEMW inactive tMEMW6 0 ns MEMW inactive to active tMEMW7 35 ns 10BASE T Transmit TXD Pair Jitter into 100 Ω Load tTTX1 8 ns TXD Pair Return to 50 mV after Last Positive Transition tTTX2 4 5 µs TXD Pair Positive Hold Time at End of Packet tTTX3 250 ns SA 19 0 SBHE CHIPSEL Valid Address MEMCS16 IN DIRECTION IN or OUT of chip MEMW S...

Страница 117: ...er Sense tTRX4 1 2 bits Carrier Sense Deassertion Delay tTRX5 270 ns 10BASE T Link Integrity First Transmitted Link Pulse after Last Transmitted Packet tLN1 8 16 24 ms Time Between Transmitted Link Pulses tLN2 8 16 24 ms Width of Transmitted Link Pulses tLN3 60 100 200 ns Minimum Received Link Pulse Separation tLN4 2 7 ms Maximum Received Link Pulse Separation tLN5 25 150 ms Last Receive Activity ...

Страница 118: ...Center and Boundary Jitter in Data tARX2 18 ns Carrier Sense Assertion Delay tARX3 240 ns Invalid Preamble Bits after Carrier Sense Asserts tARX4 1 2 bits Carrier Sense Deassertion Delay tARX5 150 250 ns AUI Collision CI Pair Cycle Time tACL1 85 100 115 ns CI Pair Rise and Fall Times tACL2 10 ns CI Pair Return to Zero from Last Positive Transition tACL3 160 ns Collision Assertion Delay tACL4 50 20...

Страница 119: ...to CSOUT high tBPROM3 40 ns EEPROM EESK Setup time relative to EECS tSKS 100 ns EECS ELCS_b Setup time wrt EESK tCCS 250 ns EEDataOut Setup time wrt EESK tDIS 250 ns EEDataOut Hold time wrt EESK tDIH 500 ns EEDataIn Hold time wrt EESK tDH 10 ns EECS Hold time wrt EESK tCSH 100 ns Min EECS Low time during programming tCS 1000 ns SA 19 0 MEMR tBPROM1 CSOUT CS tBPROM3 tBPROM2 External Boot PROM Acces...

Страница 120: ...sistors are 1 tolerance The CS8900A supports 100 120 and 150 Ω unshielded twisted pair cables The proper values of Rt and Rr for a given cable impedence are shown below Note for 3 3V operation the turns ratio on TXD and TXD is 1 2 5 rt is 8Ω for 100Ω cable and the 68pF cap changes to 560pF Cable Impedance Ω Rt Ω Rr Ω 100 24 3 49 9 120 30 1 60 4 150 37 4 75 Rt Rt CS8900A TD TD TXD TXD 1 2 RJ45 1 2 ...

Страница 121: ...tions Parameter Min Typ Max Unit Parallel Resonant Frequency 20 MHz Resonant Frequency Error CL 18 pF 50 50 ppm Resonant Frequency Change Over Operating Temperature 40 40 ppm Crystal Capacitance 18 pF Motional Crystal Capacitance 0 022 pF Series Resistance 50 Ohm Shunt Capacitance 7 pF CS8900A DO DO 1 1 DB15 3 10 Tx 4 1 1 5 12 13 6 12 V CI CI 1 1 2 9 39 2 Ω 39 2 Ω Col 0 01 uF DI DI 39 2 Ω 39 2 Ω R...

Страница 122: ... 1 60 A1 0 002 0 006 0 05 0 15 B 0 007 0 011 0 17 0 27 D 0 618 0 642 15 70 16 30 D1 0 547 0 555 13 90 14 10 E 0 618 0 642 15 70 16 30 E1 0 547 0 555 13 90 14 10 e 0 016 0 024 0 40 0 60 L 0 018 0 030 0 45 0 75 0 000 7 000 0 00 7 00 Nominal pin pitch is 0 50 mm Controlling dimension is mm JEDEC Designation MS026 100L TQFP PACKAGE DRAWING E1 E D1 D 1 e L B A1 A ...

Страница 123: ... Memory EOF End of Frame FCS Frame Check Sequence FDX Full Duplex IA Individual Address IPG Inter Packet Gap ISA Industry Standard Architecture LA ISA Latchable Address Bus LA17 LA23 LLC Logical Link Control MAC Media Access Control MAU Medium Attachment Unit MIB Management Information Base RX Receive SA Source Address or ISA System Address Bus SA0 SA19 SFD Start of Frame Delimiter SNMP Simple Net...

Страница 124: ...onger than between 20 ms and 150 ms Packet An Ethernet string of data bits that includes the Preamble Start of Frame Delimiter SFD Destination Address DA Source Address SA optional length field Logical Link Control data LLC data pad bits if needed and Frame Check Sequence FCS A packet is a frame plus the Preamble and SFD Receive Collision A receive collision occurs when the CI CI inputs are active...

Страница 125: ... when a logic 1 is written to that bit To cause the action again the host must rewrite a 1 Committed Receive Frame A receive frame is said to be committed after the frame has been buffered by the CS8900A and the host has been notified but the frame has not yet been transferred by the host Committed Transmit Frame A transmit frame is said to be committed after the host has issued a Transmit Command...

Страница 126: ...ansmit Request A Transmit Request is issued by the host to initiate the start of a new packet transmission A Transmit Request consists of the following three steps in exactly the order shown 1 The host writes a Transmit Command to the TxCMD register PacketPage base 0144h 2 The host writes the transmit frame s length to the TxLength register PacketPage base 0146h 3 The host reads BusST Register 18 ...

Страница 127: ... Notes ...

Страница 128: ...ication may be copied reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photographic or otherwise without the prior written consent of Cirrus Logic Inc Items from any Cirrus Logic website or disk may be printed for use by the user However no part of the printout or electronic files may be copied reproduced stored in a retrieval system or trans...

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