Cirrus Logic Crystal CS98000 Series Скачать руководство пользователя

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CS98000

DS525PP1

Pin

Signal Name

Type

Description

87, 83, 79, 76,
74, 71, 68, 64,
67, 70, 72, 75,
78, 80, 86, 88,
60, 56, 54, 49,
46, 44, 40, 33,
37, 42, 45, 48,
51, 55, 59. 62

M_D[31..0]

Memory Data Bus. CS98000 can use all 32 bits or can use
only M_D[15..0], in which case M_D[31..16] can be left un-con-
nected.

2, 3, 5, 6, 7, 9,
10, 11, 13, 14,
15, 16

M_A[11..0]

Memory Address Bus. Connect in order starting with M_A[0] to
all RAM address pins not already connected to M_BS_L or
M_AP. Unused upper M_A pins unconnected.

M_CKO

Memory Clock

M_CKE

Memory Clock Enable

M_BS_L

Bank Selection. Always connect to RAM BS or BS0 pin.

M_AP

Memory Auto Pre-charge. Always connect to RAM AP pin.

M_RAS_L

Memory Row Address Strobe

M_CAS_L

Memory Column Address Strobe

M_WE_L

Memory Write Enable

32, 31, 29, 28

M_DQM[3..0]

IO Mask of Data Bus M_DQM[3] -> M_D[31:24]

Table 8. SDRAM Interface

Pin

Signal Name

Type

Description

60, 56, 54, 49,
46, 44, 40, 33,
37, 42, 45, 48,
51, 55, 59. 62

M_D[15..0]

Memory Data Bus. Use M_D[7:0] for 8-bit interface

2, 3, 5, 6, 7, 9,
10, 11, 13, 14,
15, 16

M_A[11..0]

Memory Address Bus[11..0]

74, 71, 68, 64,
67, 70, 72, 75,
78, 80, 86, 88

M_D[27..16]

Memory Address Bus[23..12] For
16-bit data mode, M_D[26:16] is upper word address.
For 8-bit data mode, M_D[27:16] is upper byte address.

M_D[30]

Address decode low. Copy of address MSB.

M_D[31]

Address decode high. Compliment of address MSB.

NVM_WE_L

NVRAM Write Enable.

NVM_OE_L

ROM/NVRAM Output Enable.

Table 9. ROM/NVRAM Interface

Содержание Crystal CS98000 Series

Страница 1: ...on Overall the CS98000 Crystal DVD Processor is targeted as a market specific consumer entertainment processor empowering new product classes with the inclusion of a DVD player as a fundamental feature This integrated circuit when used with all the other Crystal mixed signal data converters DSPs and high quality factory firmware enables the conception and rapid design of market lead ing internet a...

Страница 2: ...reindevelopment and subject todevelopment changes Cirrus Logic Inc has madebest efforts toensurethat theinformation contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied No responsibility is assumed by Cirrus Logic Inc for the use of this information nor for infringements...

Страница 3: ... maximum rating 8 Electrical Characteristics 8 Table 1 Host Port Memory Map 15 Table 2 Internal IO space map 15 Table 3 CS98000 Register Map and Blocks 16 Table 4 CS98000 Registers 16 Table 5 Pin Type legend 25 Table 6 Pin assignments 26 Table 7 Miscellaneous Interface Pins 31 Table 8 SDRAM Interface 32 Table 9 ROM NVRAM Interface 32 Table 10 Video Output Interface 33 Table 11 Video Input Interfac...

Страница 4: ...device and CS98000 ATAPI TRANSACTION Symbol Description Min Typ Max Unit Tasu Address valid to H_RD 25 30 ns Tdsu Read data setup time 20 30 ns Tc Transaction cycle time 70 75 ns Tw Read or write pulse width 70 75 ns Trdh Read data hold time 5 15 ns Twdh Write data hold time 10 15 ns Ta H_RDY width 1250 ns Trd Read data valid to H_RDY valid 35 45 ns Tr H_RDY drive high to release time 5 ns Din Dou...

Страница 5: ...table show detailed timing In both Figure 3 and 4 CAS latency is programmed to 3 Figure 2 SDRAM Refresh Transaction M_CKE M_A_ 11 0 M_BS_L M_RAS_L M_CAS_L M_WE_L MD 31 0 M_DQM_ 3 0 M_AP Figure 3 SDRAM Burst Write Transaction D0 D1 D2 D3 D4 D5 D6 D7 C1 C2 C3 C4 C5 C6 C7 C0 R0 M_CKO M_A_ 11 0 M_BS_L M_RAS_L M_CAS_L M_WE_L M_D_ 31 0 M_DQM_ 3 0 M_AP Figure 4 SDRAM Burst Read Transaction D0 D1 D2 D3 D4...

Страница 6: ...ock to Out 9 ns tcch Clk High Time 4 5 ns tccl Clk Low Time 4 5 ns tmper Clk Period 10 12 2 ns tmhw Output Hold Time 3 ns tmdow Clk to Data Bus Valid 5 ns tmsuw Data Valid to Clk 3 ns MRAS MCAS MWE AP DQM0 3 MCKE MA 011 tccl tcch tmper tmco DQ0 DQ31 WRITE DQ0 DQ31 READ CLOCK tmsur tmhr tmhw tmsuw tmdow Figure 5 SDRAM Timing ...

Страница 7: ...ion Min Typ Max Unit Tdsu Video data setup time 5 ns Tdh Video data hold time 5 ns Tsysu HSYNC or VSYNC to Clock setup time 5 ns Tsyh Clock to HSYNC or VSYNC hold time 5 ns Tckl Video clock low time 14 8 22 2 ns Tckh Video clock high time 14 8 22 2 ns Tsysu Tdh Tdsu CLK27_O VDAT_ 7 0 HSYNC VSYNC Tckl Tckh Tsyh Figure 6 CS98000 Interface with Video Encoder ...

Страница 8: ...wer applied 0 70 oC PIO Power consumption on I O ring CL 35 pF 57 mA PCORE Power consumption on the core logic 620 mA PPLL Power consumption on the PLL logic 15 mA Parameter Symbol Conditions Min Typ Max Units Supply Voltage IO VDD 3 0 3 3 3 6 Volts Supply Voltage core and PLL VDD 2 25 2 5 2 75 Volts Supply Current IO IDD Normal Operating 45 mA Supply Current core and PLL IDD Normal Operating 550 ...

Страница 9: ...emote Keyboard Control Video Encoder CODEC Composite Video Phone IR S Video Audio L 3 Audio R 3 Parallel Port DAA 3 Audio DACs Power Reg Line Power Switch S PDIF FLASH 2MB SDRAM 8MB Audio ADC Video Decoder Driver Front Panel Video Audio L Audio R DVD Loader I O Chan or ATAPI Loader Hard Drive Hard drive useable with ATAPI loader Figure 7 CS98000 Typical Application ...

Страница 10: ...ry Single cycle instructions runs at 81 Mhz 3 2 3 System Controls Include several hardware lockable semaphore registers General purpose register for inter processor communication 32 bit timers for I O and other uses with pro grammable interval rates RISC 1 Instruction Cache Data Cache MMU MAC RISC 2 Instruction Cache Data Cache MMU MAC MPEG Decoder VLC Parser IDCT RAM Motion Comp System Sync STC I...

Страница 11: ... 8 Audio Interface Supports PCM I2 S and IEC 958 outputs at up to 96 KHz output rate 8 output channels 2 input channels 3 2 9 Video Input NTSC PAL video decoder input interface Built in variable down scaling handles CCIR 601 to QCIF input formats Video input image can be displayed in small window or as main picture 3 2 10 External Interface Serial I2C master and slave port 29 independent fully pro...

Страница 12: ...ed fashion with C support effectively achieving single cycle throughout There are other instructions that are de signed to help with performing MPEG1 2 decod ing The CS98000 fully supports many Real Time Operating Systems RTOS such as WindRiver OS and ATI The RISC processor co ordinates on chip multi threaded tasks as well as system activi ties such as remote control and front panel control 3 4 DS...

Страница 13: ...an be used for debug functions Interrupts can be generated on specific or generic events Infrared inputs can be filtered of glitches or stored unfiltered into memo ry Control of all the internal clocks is also possi ble Internal PLLs are used to generate the internal system and memory clocks and audio clocks of any widely used frequency 3 8 DVD ATAPI Interface The CS98000 has a programmable interf...

Страница 14: ...e ad justed to 20 18 or 16 bits to match common DAC and ADC formats or any other specific size In AC97 mode any slot can be used to interface either a modem CODEC or an audio CODEC 3 12 Video The Digital Video Interface provides flexible and powerful means of outputting digital video data to external devices in CCIR601 3 and CCIR656 YUV formats The interface directly supports NTSC PAL video encode...

Страница 15: ...F_FFFF 16 bit NVRAM write 16 Mbytes N 9C00_0000 9CFF_FFFF 16 bit NVRAM ROM 16 Mbytes Y 9D00_0000 9DFF_FFFF 8 bit NVRAM ROM 16 Mbytes Y A000_0000 A1FF_FFFF DRAM 32 Mbytes N B000_0000 B003_FFFF Internal I O 256 Kbytes N B400_0000 BCFF_FFFF 16 bit NVRAM write 16 Mbytes N BC00_0000 BCFF_FFFF 16 bit NVRAM ROM 16 Mbytes N BD00_0000 BDFF_FFFF 8 bit NVRAM ROM 16 Mbytes N C000_0000 FFFF_FFFF DRAM mapped Y ...

Страница 16: ...Input Scaler 00Axx Picture in picture 00Bxx Video Processor 00Cxx Subpicture Display 00Dxx On screen Display 00Exx PCM In Out 02xxxx RISC_0 03xxxx RISC_1 Table 3 CS98000 Register Map and Blocks Address Type Function Register Name 000 R W General Command 010 R W General InterProc_Comm_Register_0 014 R W General InterProc_Comm_Register_1 018 R W General InterProc_Comm_Register_2 10C R W General Inte...

Страница 17: ...ve_Edge_Mask 105C R W General GenIOMIS_Negative_Edge_Mask 1060 R W General GenIOMIS_Level_Mask 1064 R W General GenIOMIS_Mode Register 1068 RO General GenIODVD_Read_Data 106C R W General GenIODVD_Write_Data 1070 R W General GenIODVD_Tri_State_Enable 1074 RO General GenIOHST_Read_Data 1078 R W General GenIOHST_Write_Data 107C R W General GenIOHST_Tri_State_Enable 068 R W General I2C_Mstr_Read_Coman...

Страница 18: ...General Timer_0 0C4 R W General Timer_1 0C8 R W General Timer_2 0CC R W General Timer_3 0D0 R W General Timer_Control 0D4 RO General Performance_Monitor_Count 0D8 R W General Timer_M_Over_N 0E0 R W General IR_Control 0E4 R W General IR_Dram_Start_Address 0E8 R W General IR_Dram_End_Address 0EC RO General IR_Dram_Write_Address 0F0 R W General PLL_Control_Register1 10F0 R W General Low_Power_Clock_C...

Страница 19: ...Control 308 RO DMA DMA_Status 30C R W DMA Xfer_Byte_Cnt 310 R W DMA Dram_Byte_Start_Addr 314 R W DMA Sram_Byte_Start_Addr 318 R W DMA Fifo_Start_Rd_Addr 31C R W DMA Fifo_Start_Wr_Addr 328 R W DMA Search_Control 32C RO DMA Search_Status 330 R W DMA Fifo_End_Rd_Addr 334 R W DMA Fifo_End_Wr_Addr 338 R W DMA Lines_and_Skip 33C R W DMA Byte_Mask_Pattern 400 R W CD DVD DVD1 _Control 404 R W CD DVD DVD1 ...

Страница 20: ...R W SER DCI Slot12_Register_Data 580 R W SER DCI Out_fifo_int 584 R W SER DCI In_fifo_int 588 R W SER DCI Rate_Control 600 WO DSP DSP_Boot_Code_Start_Address 604 WO DSP DSP_Run_Enable 6XX RO DSP DSP_Program_CntRun_Status 700 R W Sync Control Audio_Sync_Control 704 R W Sync Control Video_Sync_Control 708 RO Sync Control Video_Sync_Status 70C R W Sync Control Wait_Line 710 R W Sync Control Frame_Per...

Страница 21: ...ress 80C R W MPEG Vid Decoder MPEG_Video_FIFO_End_Address 810 RO MPEG Vid Decoder MPEG_Video_FIFO_Current_Address 814 RO MPEG Vid Decoder MPEG_Video_Horiz_Pan_Vector 818 WO MPEG Vid Decoder MPEG_Video_FIFO_Add_Bytes 81C RO MPEG Vid Decoder MPEG_Video_FIFO_Curr_Bytes 820 R W MPEG Vid Decoder MPEG_Video_FIFO_Interrupt_Bytes 824 RO MPEG Vid Decoder MPEG_Video_FIFO_Total_Bytes 828 RO MPEG Vid Decoder ...

Страница 22: ...play_ActiveX B0C R W Video Processor Display_ActiveY B10 R W Video Processor Blank_Color B14 R W Video Processor Internal_Hsync_Count B18 R W Video Processor Internal_Vsync_Count B1C R W Video Processor Horizontal_Y_Offset B20 R W Video Processor Horizontal_UV_Offset B24 R W Video Processor Vertical_Offset B28 R W Video Processor Video_Line_Size B2C R W Video Processor Frame_Buffer_Base B30 R W Vi...

Страница 23: ...bpicture Subpicture_Color9 C28 R W Subpicture Subpicture_Color10 C2C R W Subpicture Subpicture_Color11 C30 R W Subpicture Subpicture_Color12 C34 R W Subpicture Subpicture_Color13 C38 R W Subpicture Subpicture_Color14 C3C R W Subpicture Subpicture_Color15 C40 R W Subpicture Subpicture_DCI_Address C44 R W Subpicture Subpicture_HLI_Address C50 R W Subpicture Subpicture_Control C54 R W Subpicture Subp...

Страница 24: ... W PCM PCM_Out_FIFO_Interrupt_Address E14 RO PCM PCM_Out_FIFO_Current_Address E18 R W PCM SPDIF_Channel_Status E20 R W PCM PCM_Input_Control E24 R W PCM PCM_In_FIFO_Start_Address E28 R W PCM PCM_In_FIFO_End_Address E2C R W PCM PCM_In_FIFO_Interrupt_Address E30 R W PCM PCM_Out_FIFO_Interrupt_Address2 E34 R W PCM PCM_Out_FIFO_Interrupt_Address3 E38 RO PCM PCM_In_FIFO_Current_Address E3C RW PCM SPDIF...

Страница 25: ... B4SU Bi direction 4mA drive with pull up and schmitt trigger Pwr 2 5V or 3 3V power supply voltage Gnd Power supply ground Name_N Low active Name_L Low active Table 5 Pin Type legend H_D_ 15 0 H_CS_ 3 0 H_A_ 4 0 H_ALE H_RD H_WR H_CKO H_RDY VIN_D 7 0 VIN_HSNC VIN_VSNC VIN_CLK VIN_FLD M_A_ 11 0 M_BS_L M_D_ 31 0 M_DQM_ 3 0 M_RAS_L M_CAS_L M_WE_L M_AP M_CKE M_CKO NVR_OE_L NVR_WR_L HSYNC VSYNC CLK27_O...

Страница 26: ...s 6 O ROM NVRAM Address 6 O 10 M_A_5 O8 SDRAM Address 5 O ROM NVRAM Address 5 O 11 M_A_4 O8 SDRAM Address 4 O ROM NVRAM Address 4 O 12 GPIO_D17 B4U GenioDVD 17 B 13 M_A_3 O8 SDRAM Address 3 O ROM NVRAM Address 3 O 14 M_A_2 O8 SDRAM Address 2 O ROM NVRAM Address 2 O 15 M_A_1 O8 SDRAM Address 1 O ROM NVRAM Address 1 O 16 M_A_0 O8 SDRAM Address 0 O ROM NVRAM Address 0 O 17 GPIO_D19 B4U GenioDVD 19 B ...

Страница 27: ...13 B 55 M_D_2 B8U SDRAM Data 2 B ROM NVRAM Data 2 B 56 M_D_14 B8U SDRAM Data 14 B ROM NVRAM Data 14 B 57 GPIO_D6 B4U GenioDVD 6 B 58 VSS_IO Gnd I O Ground 59 M_D_1 B8U SDRAM Data 1 B ROM NVRAM Data 1 B 60 M_D_15 B8U SDRAM Data 15 B ROM NVRAM Data 15 B 61 GPIO_D7 B4U GenioDVD 7 I B 62 M_D_0 B8U SDRAM Data 0 B ROM NVRAM Data 0 B 63 VSS_CORE Gnd Core Ground 64 M_D_24 B8U SDRAM Data 24 B ROM NVRAM Add...

Страница 28: ...B 95 H_RDY B4 Host Ready I DVD Data Ready O 1 96 VSS_IO Gnd I O Ground 97 H_A_2 B4 Host Address 2 O GenioHst 10 B 1 98 GPIO_H16 B4U GenioHst 16 B 99 H_A_1 B4 Host Address 1 O GenioHst 9 B 1 100 H_A_0 B4 Host Address 0 O GenioHst 8 B 1 101 H_CS_1 B4 Host Chip Select 1 O DVD Error I 1 102 H_A_4 B4 Host Address 4 O GenioHst 12 B 1 103 VSS_CORE Gnd Core Ground 104 VSS_PLL Gnd PLL Ground 105 VDD_PLL Pw...

Страница 29: ...nioMis 2 B 134 H_D_0 B4 Host Data 0 B DVD Data 0 I 1 135 AUD_DO_0 O4 Audio Out Data 0 O 136 AUD_DO_1 B4 Audio Out Data 1 O GenioMis 1 B 137 AIN_BCK IU Audio In Bit Clock I 138 VSS_CORE Gnd Core Ground 139 AIN_LRCK IU Audio In LR Clock I 140 AIN_DATA B4U Audio In Data I GenioMis 0 B 141 VDD_CORE Pwr Core Power 2 5V 142 CDC_DI IU Serial CODEC Data In I 143 VSS_IO Gnd I O Ground 144 CDC_DO T4 Serial ...

Страница 30: ... Ground 177 AUD_DO_3 B4U Audio Out Data 3 O General Purpose IO 1 B 178 VDD_CORE Pwr Core Power 2 5V 179 VIN_D3 B4U Video Input Data 3 I GenioMis 19 B 180 VDD_IO Pwr I O Power 3 3V 181 GPIO_2 B4U General Purpose IO 2 B 182 VSS_IO Gnd I O Ground 183 GPIO_3 B4U General Purpose IO 3 B 184 VIN_D4 B4U Video Input Data 4 I GenioMis 20 B 185 GPIO_4 B4U General Purpose IO 4 B 186 SCL B4U I2C Clock B Genera...

Страница 31: ...t could be either ROM NVRAM FLASH or EEPROM or any combina tion of those This interface can also connect to SRAM that would emulate a ROM on a development system The bus width is eight or 16 bits Except for the NVM_WE_L and NVM_OE_L pins all these pins are shared with the DRAM interface which op erates simultaneously with the ROM NVRAM inter face 199 GPIO_15 B4U General Purpose IO 15 B 200 VSS_COR...

Страница 32: ...rge Always connect to RAM AP pin 24 M_RAS_L O Memory Row Address Strobe 25 M_CAS_L O Memory Column Address Strobe 27 M_WE_L O Memory Write Enable 32 31 29 28 M_DQM 3 0 O IO Mask of Data Bus M_DQM 3 M_D 31 24 Table 8 SDRAM Interface Pin Signal Name Type Description 60 56 54 49 46 44 40 33 37 42 45 48 51 55 59 62 M_D 15 0 B Memory Data Bus Use M_D 7 0 for 8 bit interface 2 3 5 6 7 9 10 11 13 14 15 1...

Страница 33: ...Name Type Description 154 CLK27_O O 27 Mhz Clock Output 159 HSYNC B Horizontal Sync Output when the CS98000 is the video master input when the video encoder is master 162 VSYNC B Vertical Sync Output when the CS98000 is the video mas ter input when the video encoder is master 173 172 170 169 167 166 165 163 VDAT 7 0 O Video Data Output 7 0 in Cb Y Cr Y format Table 10 Video Output Interface Pin Si...

Страница 34: ...ata Out 0 136 AUD_DO_1 O Audio Serial Data Out 1 133 AUD_DO_2 O Audio Serial Data Out 2 177 AUD_DO_3 O Audio Serial Data Out 3 204 SPDIF_O O S PDIF Output 137 AIN_BCK I Audio Input Bit Clock The CS98000 can be programmed to use the Audio Output function s internally generated bit clock in which case this pin is not required 139 AIN_LRCK I Audio Input Left Right Clock The CS98000 can be pro grammed...

Страница 35: ...so be re defined and GPIO s 6 12 Power and Ground The CS98000 requires 3 different types of power supplies PLLs internal logic and IO pins The PLLs and internal logic use 2 5 V power supply The IO pins use 3 3 V power supply and are 5 V input tolerant Pin Signal Name Type Description 111 115 101 106 H_CS 3 0 O Host Chip Select 3 0 The host master can be pro grammed to use a different protocol for ...

Страница 36: ...r 106 H_CS_0 I DVD data start sector signal from loader 101 H_CS_1 I DVD data error signal from loader 95 H_RDY O DVD data ready signal to loader 93 H_WR I DVD data enable signal from loader 92 H_RD I DVD data clock from loader Table 15 DVD I O Channel Interface Pin Signal Name Type Description 26 17 4 12 8 150 151 152 155 65 69 73 77 61 57 50 47 43 39 34 30 GPIO_D 20 0 B 21 General purpose I O s ...

Страница 37: ...66 84 108 129 141 161 178 203 VDD_CORE 2 5V for internal core logic 20 38 91 131 180 VDD_IO 3 3V for I O s 104 157 208 VSS_PLL Ground for internal PLLs 36 63 82 103 126 138 158 176 200 VSS_CORE Ground for internal core logic 18 35 58 96 119 143 182 VSS_IO Ground for I O s Table 17 Power and Ground ...

Страница 38: ...IONS 1 52 53 104 105 156 157 208 0 50 0 05 0 22 0 05 30 6 0 2 28 00 0 05 2 8 00 0 0 5 3 0 6 0 2 DETAIL A 0 MIN R0 20 1 3 0 1 R0 15 10 15 0 15 TY P 0 20 BASE METAL WITH PLATING 0 15 TY P 0 50 0 1 5 0 2 MIN 0 35 0 1 Detail A 3 35 0 05 3 80 MAX ...

Страница 39: ... Notes ...

Страница 40: ......

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