10
DS723DB1
CDB43L21
2.3
Register Maps Tab
The Advanced Register Debug tab provides low-level control of the CS43L21 individual register settings.
Register values can be modified bit-wise or byte-wise. For bit-wise, click the appropriate push-button for the
desired bit. For byte-wise, the desired hex value can be typed directly into the register address box in the
register map. The “FPGA” and “GPIO” tabs may be ignored.
Figure 3. Register Maps Tab - CS43L21
Содержание CDB43L21
Страница 16: ...16 DS723DB1 CDB43L21 7 CS43L21 SCHEMATICS Figure 10 CS43L21 and Analog I O Schematic Sheet 1 ...
Страница 17: ...DS723DB1 17 CDB43L21 Figure 11 S PDIF I O Schematic Sheet 2 ...
Страница 18: ...18 DS723DB1 CDB43L21 Figure 12 FPGA Schematic Sheet 3 ...
Страница 19: ...DS723DB1 19 CDB43L21 Figure 13 Level Shifters I O Stake Header Schematic Sheet 4 ...
Страница 20: ...20 DS723DB1 CDB43L21 Figure 14 Control Port I O Schematic Sheet 5 ...
Страница 21: ...DS723DB1 21 CDB43L21 Figure 15 Power Schematic Sheet 6 ...
Страница 22: ...22 DS723DB1 CDB43L21 8 CDB43L21 LAYOUT Figure 16 Silk Screen CDB43L21 CS43L21 CS43L21 CS43L21 ...
Страница 23: ...DS723DB1 23 CDB43L21 Figure 17 Top Side Layer ...
Страница 24: ...24 DS723DB1 CDB43L21 Figure 18 Bottom Side Layer ...
