CDB4272
8
1.9
External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the
headers J26, J32, J17, and J24.
The 10-pin header, J26, allows the user bidirectional access to MCLK, SCLK, and LRCK. The
direction of these signals is set using S1 (see Table 2 for switch control options) or the control
port GUI. Also accessible from this header is a buffered version of the SDOUT signal from
the CS4272, and a buffered input which, using S1 or the GUI, can be configured to drive the
CS4272 SDIN pin. Care should be taken to ensure that the crystal (Y2) is removed when the
board is configured to receive MCLK from this header.
The 2-pin header, J17, allows the user to supply the CS8406 with an external data source.
This option is available through the control port GUI and may be asserted by setting the
CS8406 data source to “Header”.
The 2-pin header, J24, supplies the user with a buffered version of the SDOUT signal gener-
ated by the CS8416. This may be used, for instance, to route received S/PDIF data off-board
for processing before introducing it at the SDIN position on J26.
The 6-pin header, J32, allows the user bidirectional access to the SPI/I
2
C control signals. The
signals on J32 default to outputs. When a jumper is placed across J34, the header (J32) may
be used as an input. When set as an input, the control signals on J32 are routed to the cor-
responding control pins on the CS4272 and external control signals may be applied.
1.10 Power
Power must be supplied to the evaluation board through at least three binding posts, +5.0 V
(J1), +18.0 V (J6), and -18.0 V (J7). Jumper J10 allows the user to connect the VA supply of
the CS4272 to a fixed +5.0 V supply or to another separate binding post (J5). Jumpers J8
and J9 connect the VL and VD supply, respectively, to a fixed +5.0 V or +3.3 V supply or to
two separate binding posts (J2 and J3) for variable voltage settings. All voltage inputs must
be referenced to the single black banana-type ground connector (see Figure 15).
It should be noted that devices other than the CS4272 are powered from the VL supply and
therefore VL must be limited to a minimum of 3.3 V.
WARNING:Please refer to the CS4272 data sheet for allowable voltage levels.
1.11 Grounding and Power Supply Decoupling
The CS4272 requires careful attention to power supply and grounding arrangements to opti-
mize performance. Figure 5 provides an overview of the connections to the CS4272,
Figure 16 shows the component placement, Figure 17 shows the top layout, and Figure 18
shows the bottom layout. The decoupling capacitors are located as close to the CS4272 as
possible. Extensive use of ground plane fill in the evaluation board yields large reductions in
radiated noise.
Содержание CDB4272
Страница 16: ...CDB4272 16 5 SCHEMATICS AND LAYOUT Figure 6 Hierarchy Schematic Sheet 1 ...
Страница 17: ...CDB4272 17 Figure 7 CS4272 Schematic Sheet 2 ...
Страница 18: ...CDB4272 18 Figure 8 Analog Input Schematic Sheet 3 ...
Страница 19: ...CDB4272 19 Figure 9 Analog Output Schematic Sheet 4 ...
Страница 20: ...CDB4272 20 Figure 10 CS8416 S PDIF Receiver Schematic Sheet 5 ...
Страница 21: ...CDB4272 21 Figure 11 CS8406 S PDIF Transmitter Schematic Sheet 6 ...
Страница 22: ...CDB4272 22 Figure 12 Board Setup Schematic Sheet 7 ...
Страница 23: ...CDB4272 23 Figure 13 PCM Header Schematic Sheet 8 ...
Страница 24: ...CDB4272 24 Figure 14 Control Port Schematic Sheet 9 ...
Страница 25: ...CDB4272 25 Figure 15 Power Schematic Sheet 10 ...
Страница 26: ...CDB4272 26 Figure 16 Component Placement and Reference Designators ...
Страница 27: ...CDB4272 27 Figure 17 Top Layer ...
Страница 28: ...CDB4272 28 Figure 18 Bottom Layer ...
Страница 29: ...CDB4272 29 6 APPENDIX Complete Analog Input Buffer Schematic Figure 19 Complete Analog Input Buffer Schematic ...
