EGS5 Hardware Interface Description
3.15 Audio Interfaces
75
EGS5_HD_v02.004
Page 68 of 123
2012-02-09
Confidential / Released
The timing of a PCM
short frame
. The 16-bit TXDAI and RXDAI data is
transferred simultaneously in both directions during the first 16 clock cycles after the frame
sync pulse. The duration of a frame sync pulse is one BITCLK period, starting at the rising edge
of BITCLK. TXDAI data is shifted out at the next rising edge of BITCLK. RXDAI data (i.e. data
transmitted from the host application to the module's RXDAI line) is sampled at the falling edge
of BITCLK.
Figure 29:
Short Frame PCM timing
The timing of a PCM
long frame
is shown in
. The 16-bit TXDAI and RXDAI data is
transferred simultaneously in both directions while the frame sync pulse FS is high. For this rea-
son the duration of a frame sync pulse is 16 BITCLK periods, starting at the rising edge of BIT-
CLK. TXDAI data is shifted out at the same rising edge of BITCLK. RXDAI data (i.e. data
transmitted from the host application to the module's RXDAI line) is sampled at the falling edge
of BITCLK.
Figure 30:
Long Frame PCM timing
