DSB75 Development Support Board Rev. B1 Hardware Description
Confidential / Released
DSB75_hd_v12
Page 45 of 96
2008-08-26
3.9 I²C
Interface
The GSM module is the bus master device. The I2CDAT and I2CCLK lines have to be
connected on the slave side to a positive supply voltage via a current source or pull-up
resistor.
The number of interfaces connected to the bus is only dependent on the bus capacity limit of
400pF.
Each device connected to the bus is software addressable by a unique address, and simple
master/slave relationships exist at all times.
On the DSB75 both I²C lines can alternatively be used as SPI interface lines (if supported by
the GSM module, see section 3.11).
The I²C interface lines are available on the DSB75 at the 10 pin header X511. A level shifter
V500/V501 converts from 3V up to 5V logic. The 3V logic lines are connected directly to the
pins of the pin header X511, if switches S500 and S501 are set to position 1.
Attention:
Two external pull-up resistors must be installed in the host application. There are
no on-board pull-up resistors.
The 5V compliant lines are an alternative to the 3V lines available on the X511 pin header.
To use 5V lines, set the switches S500 and S501 to position 3.
The two logic voltages 5V0 and VDD are available at the X511 pin header for supplying the
external I²C device driver.
For a simple test facility a 128kBit EEPROM device (D500) with adjustable address area
(S502 - S504) is implemented. Accordingly the switches S500 and S501 are set to position 3
(see Figure 23).
The LED V503 indicates that I2CCLK line is active (low).
The LED V504 indicates that I2CDAT line is active (low).
Figure 23 shows the simplified interface schematic.
Figure 24 shows the placement of the I²C switches and the pin location.
Electrical characteristics are specified in section 8.
