CHAINTECH 6OIV, Руководство пользователя

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Har dware Setup
21
2-5 Main Memory Configuration
The DRAM memory system consists of three banks and the memory size ranges from
16~512 MBytes. It does not matter which bank you want to install first.
DRAM Specifications
DIMM type : 3.3V, unbuffered, registered, 64/72-bit SDRAM with SPD*
Module size: Single/double-side 16/32/64/128/256 MBytes
Parity : Either parity or non-parity
This mainboard supports up to 2 double sided or 2 single sided DIMMs at
133MHz system memory bus.
This mainboard supports 3.3v, unbuffered, 4-clock, SDRAM DIMM only.
Buffered, 5V, or 2-clock SDRAM DIMMs should not be used.
Due to loading anomalies, using DIMM with an 'n x 4' DRAM base on this
mainboard is not recommended. For example, a DIMM that uses sixteen
16Mb x 4 devices should not be used.
SPD (Serial Presence Detect)
This is an EPROM that contains speed and design information about the memory
module. The mainboard queries the module and makes adjustments to system
operation based on what it finds.
ECC DRAM Capability
This mainboard can be configured to support ECC (Error Check and Correct)
function when utilizing parity DIMM modules. To utilize the chipset's ECC features,
you must use a 72-bit DIMM module.These modules are automatically detected
during bootup. However, the user must configure the DRAM Data Integrity Mode
to "ECC" in BIOS's SeePU&Chipset Features Setup menu to enable the ECC function.
ECC detects double bit errors and detects and corrects single bit memory errors on
the fly without user intervention. Errors may be generated by a defective memory
module, conflicting memory speeds between different banks, DMA, etc.
FSB Freq. (MHz) System Memory Bus Freq. (MHz)
66 100
100 100
133 100
133 133