User's Manual
28
3-3 Chipset Features Setup
By choosing the Chipset Features Setup option from the CMOS SETUP UTILITY
menu(Figure 3-1), the screen below is displayed. This sample screen contains the
manufacturer's default values for the mainboard.
All of the above settings have been determined by the mainboard manufacturer
and should not be changed unless you are absolutely sure of what you are
doing. Explanation of the DRAM timing and chipset features setup is lengthy,
highly technical and beyond the scope of this manual. Below are abbreviated
descriptions of the functions in this setup menu. You can look on the world
wide web for helpful chipset and RAM configuration information including
AWARD's web site at http://www.award.com.
ROM PCI / ISA BIOS (2A5IMC39)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Figure 3-4 Chipset Features Setup Screen
:Select Item
PU/PD/+/-
: Modify
(Shift) F2
: Color
ESC : Quit
F1
: Help
F5
: Old Values
F7
: Load Setup Defaults
System BIOS Cacheable : Enabled
Video BIOS Cacheable : Disabled
Memory Hole at 15M-16M : Disabled
DRAM Controller 1 T WR : Disabled
DRAM Controller 1 T RD : Enabled
PCI Post Write Buffer : Disabled
PCI Delayed Transaction : Disabled
Auto Detect DIMM/PCI Clk : Disabled
Spectrum Spread : Disabled
Flash BIOS Protection : Disabled
Hardware Reset Protect : Disabled
Refresh Rate Control : 15.6us
º Ref/Act Command Delay : 6T
º Refresh Queue Depth : 12
º RAS Precharge Time : 3T
º RAS to CAS Delay : 3T
º ISA Bus Clock Frequency : PCICLK/4
º Starting Point of Paging : 1T
º NA# Enable : Enabled
º L2 Cache Burst RD Cycle : Delay 1 T
º IO Cycle NA# : Enabled
º Asyn/Sync ModeCPU/DRAM : Asynchronous
º SDRAM CAS Latency : 3T
º SDRAM WR Retire Rate : X-1-1-1
º PCI Peer Concurrency : Enabled
º Read Prefetch Memory RD : Enabled
º Assert TRDY After Prefet : 2 QWs
º CPU to PCI Burst Mem. WR : Enabled
º CPU to PCI Post Write : Enabled
º
AGP Aperture Size : 64MB
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