— 13 —
Pin No.
Name
In/Out
Description
1
VSS1
In
GND terminal
2
OSO
Out
Clock out
3
OSI
In
Clock in
4
VL1
In
6V input
5~10
A0~3,A14,15
In
Address input
11
FE
In
Chip select signal from CPU
12
CS1
In
Chip select signal from CPU
13
CS2
In
Chip select signal from CPU
14
CS3
In
Chip select signal from CPU
15
OEI
In
Output enable signal from CPU
16
VSS(GND)
In
GND terminal
17
VH1(VCC)
In
9V input
18
TXI
In
Transmission data input from CPU
19
WEI
In
Write enable signal from CPU
20
GC
In
GC signal from CPU
21
IO0
In/Out
Data bus line
22
DT
In
DT signal input
23
IO1
In/Out
Data bus line
24
VIN
In
Power ON signal from CPU (V2ON)
25
IO2
In/Out
Data bus line
26
KON
Out
Switch control signal
27
IO3
In/Out
Data bus line
28
VOB
Out
Inverted signal for VIN
29
IO4
In/Out
Data bus line
30
INT
Out
Interrupt signal
31
VH2(VCC)
In
9V input
32
VL2(VLL)
In
6V input
33
VSS(GND)
In
GND terminal
34
BBC
Out
Not used
35
PDN
In
Power down detection input
36
IO5
In/Out
Data bus line
37
RLD
Out
Not used
38
RA15
Out
Address bus output
39
IO6
In/Out
Data bus line
40
RA16
Out
Inverted signal for VIN
41
IO7
In/Out
Data bus line
42
RA17
Out
Address bus output
43
RA18
Out
Address bus output
44
MS3
Out
Not used
45
RA19
Out
Not used
46
RA20
Out
Not used
47
R15
Out
Address bus
48
VSS(GND)
In
GND terminal
49
VH3(VCC)
In
9V input
50
VDD1(VLL)
In
6V input
51
R16
Out
Address bus
52
R17
Out
Address bus
53
MSO
Out
Chip enable signal for ROM
54
MS4
Out
Chip select signal for RAM (Not used)
55
MS1
Out
Not used
56
MS5
Out
Not used
Gate array pin descriptions (SSC2571F0A): Used in SF-7900E
Содержание LX-552A
Страница 1: ...SF 7900E LX 552A SF 8900 LX 552I J R with price without price SF 7900E JAN 1995...
Страница 25: ...24 Main PCB SF8900...
Страница 26: ...25 Display PCB...
Страница 27: ...26 Key Matrix...
Страница 28: ...27 Key Matrix Display side...
Страница 32: ...MA0400751A...
