Canon Color Bubble Jet BJC-1000 Series, Руководство по обслуживанию

Страница: 84 / 126

Part 4: Technical Reference
4-26
BJC-1000
4.2.2 Logic section components
1) MPU & Printer controller (IC1)
The MPU & Printer controller contains a 16-bit CPU, 1K-bit RAM, 20-bit address bus
port, 16-bit data bus port, stepping motor controller, A-D converter, interface
controller, DRAM controller, buffer controller, print head controller, I/O port, and
other components.
MPU & Printer controller is synchronized with 16 MHz and 22.11 MHz external clock
input.
Built-in CPU
The 16-bit CPU generates the 8 MHz clock from the 16 MHz external clock input and
is synchronized with the clock.
Address bus
The 20-bit address bus port is connected to an 8 M-bit control ROM and printer
controller.
Data bus
Like the address bus, the 16-bit data bus port is connected to the 8 M-bit control
ROM.
Stepping motor controller
The stepping motor controller outputs the carriage motor's single- and two-phase
exciter drive signal and paper feed motor's two-phase exciter drive signal.
The stepping motor controller switches the carriage motor with the 5-step peak
current value for optimum driving. The stepping motor controller outputs the
switching control signal to the carriage motor driver.
A-D converter
The A-D converter digitally converts the following external analog signals
received/sent through the I/O port to enable them to be detected by the MPU &
printer controller:
AN0: The printer's internal temperature is detected by the thermistor on the logic
board.
AN1: It detects whether the BJ cartridge is installed in the printer, or not.
AN2: It monitors the VH voltage which drives the head of the cartridge.
AN3: The head rank is detected by the rank resistor in the BJ cartridge.
Interface controller
The interface controller receives from the computer, 8-bit parallel data which is
synchronized with the data strobe pulse (STROBE) through the BUSY/ACKNLG
handshake. It also controls other interface signals.
DRAM controller
The DRAM controller controls the 1 M bit DRAM's 8-bit addressbus and 16-bit data
bus and also executes read/write control, RAS/CAS control, and refresh control.