C&T Solution CT-XHW0X, Руководство пользователя

Страница: 34 / 78

CT-XHW0X Intel 4th Gen Core Processor i7/i5/i3/Celeron Industrial Mini-ITX MB
３４
Signal I/O Description
GPO[0:3] O
General purpose output pins. Upon a hardware
reset, these outputs should be low.
GPI[0:3] I
General purpose input pins. Pulled high
internally on the Module.
4.13.1 GPIO Configuration
4.13.1.1 Board Design
PIN# GPIO# Default Configuration
1 VCC3
2 GND
3 DIO_PH_OUT0 GPO0
4 DIO_PH_IN0 GPI0
5 DIO_PH_OUT1 GPO1
6 DIO_PH_IN1 GPI1
7 DIO_PH_OUT2 GPO2
8 DIO_PH_IN2 GPI2
9 DIO_PH_OUT3 GPO3
10 DIO_PH_IN3 GPI3
Notes
1. Output pin default setting is “ HIGH”
GPIO function is provided by a Fintek F81866A IC, and it can be accessed
through its GPIO index/data port. The index port is the base a0 and
the data port is the base a1. To access the GPIO register, write index
to the index port, and then read/write from/to data port. The configuration on
CT-XHW0X is described as below.
Index Port 0xA00
Data Port 0xA01
4.13.1.2 Registers Description
4.13.1.2.1 GPIO Input/Output Select

GPIO8x Configuration Registers
(Index port=0xA00, Data port=0xA01, Offset=0x88)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPO3 GPO2 GPO1 GPO0 GPI3 GPI2 GPI1 GPI0
Note.
Bit X = 0 means Input Mode