Campbell SDM-SW8A, Инструкция по эксплуатации

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SDM-SW8A Switch Closure Input Module
Signal Magnitude - The signal magnitude should range from 0 - 0.9 V low, to
4 - 5 V high, or the signal should be centered around 2.5 V with a minimum 8
V peak to peak magnitude. When the magnitude is 0 V to greater than 5 V, the
wave form begins to distort, resulting in less accurate duty cycle information.
9. Theory of Operation
The Switch Closure Input Module uses a 63705 microprocessor to sample the
8 ports and communicate with the datalogger. The processor is in a low power
"Wait" mode except when interrupted.
An internal timer interrupts the processor approximately every 2 milliseconds
to sample the input ports. At this time, for each port, the duty cycle
accumulator is updated, and the transition counter is incremented if the state
represents a positive transition from the previous state.
C3, driven high by the datalogger, also interrupts the SW8A. The SW8A
prepares to receive an 8 bit byte (consisting of address in the most significant
nibble and command in the least significant nibble with the least significant bit
always a 1) from the datalogger. The datalogger drives C2 as a clock line and
C1 as a serial data out line. The datalogger shifts out each bit (LSB first) on
the falling edge of the clock; the Switch Closure Module shifts in each bit on
the rising edge of the clock.
When all 8 bits are received by the SW8A, the SW8A is again interrupted by
its serial communication interface. If the address part of the byte received
equals the jumpered address, the SW8A executes the command part, providing
it is valid. For Function Options 1 and 2, the module receives another byte
containing Reps and Channel information from the datalogger. For a valid
address and command, the SW8A prepares to return a code byte as
acknowledgment to the datalogger. Except for the 21X, the datalogger
switches C1 to an input and after 2 milliseconds clocks back the code byte
from the SW8A. If the code byte is correct, the datalogger knows the
addressed SW8A is present. The 21X works similarly, except the data from
the SW8A is input to single ended analog channel 1, not C1.
Depending on the Command, Reps, and Channel information, the module will
shift out one or more bytes to the datalogger, again using C2 as a clock driven
by the datalogger. The module shifts out each bit on the falling edge of the
clock; the datalogger reads each bit on the rising edge of the clock.
Each time an entire byte is transmitted to the datalogger, the SW8A is
interrupted and prepares to send the next byte, if any. When all requested
bytes have been sent, the SW8A disables its serial communication interface
and waits for both C3 and C2 to be driven low by the datalogger. When this
happens, the SW8A prepares again to start a new command cycle.
An important feature of the module is its watchdog counter. The counter pulls
the processor momentarily into reset if the count gets too high. The counter
counts the C2 clock transitions. Under normal operating conditions, the
processor resets the counter. If the processor is "bombed," it will not reset the
counter. As the datalogger makes requests of the Switch Closure Module, the
counter increments to the point where it resets the processor; the module will
then start operating correctly again.
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