Cameron KS21TK305A, Руководство по обслуживанию

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SERVICE MANUAL
25
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WatchDog Timer
•
UART, SAD and PWMs
To enter Idle mode the IDL bit in the PCON register must be set. The WatchDog timer must be
disabled prior to entering Idle to prevent the device being reset. It is advice to use the RCP (Remote
Control Pre-processor) during the Idle mode to reduce the false interrupt wake-up of 80c51 in order
to achieve the low power saving mode. The CPU state is frozen along with the status of all SFRs,
internal RAM contents are maintained, as are the device output pin values, but the contents of
Display memory are lost. Since the output values on RGB and VDS are maintained the Display
output must be disabled before entering this mode.
There are three methods available to recover from Idle:
•
Assertion of any enabled interrupt will cause the IDL bit to be cleared by hardware, thus
terminating Idle mode. The interrupt is serviced, and following the instruction RETI, the next
instruction to be executed will be the one after the instruction that put the device into Idle mode.
•
A second method of exiting Idle is via an Interrupt generated by the SAD DC Compare circuit.
When TCG -Controller is configured in this mode, detection of an analogue threshold at the input
to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above,
the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will
be the one following the
instruction that put the device into Idle.
•
The third method of terminating idle mode is with a power on reset. Reset defines all SFRs and
Display memory to a pre-defined state, but maintains all other RAM values. Code execution
commences with the program counter set to
“
0000
”
.
1.6.2.3 Power down mode
In Power Down mode the XTAL oscillator is running still. The contents of all SFRs and Data
memory are maintained, however, the contents of the Display memory are lost. The port pins
maintain the values defined by their associated SFRs. Since the output values on RGB and VDS are
maintained the Display output must be made inactive before entering Power Down mode.
The power down mode is activated by setting the PD bit in the PCON register. It is advised to
disable the WatchDog timer prior to entering Power down. Recovery from Power-Down takes
several milli-seconds as the oscillator must be given time to stabilize.
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