CAES SPARC V8, Руководство пользователя

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LEON-XCKU-EX-UM
Jan 2022, Version 1.1 7
LEON-XCKU-EX
Cobham Gaisler AB
Kungsgatan | SE-411 19 | Goteborg | Sweden
+46 31 7758650 | www.caes.com/gaisler
3 Architecture
3.1 Cores
The common architecture is based on cores from the GRLIB IP library. The vendor and device identi -
fiers for each core can be extracted from the plug & play information. The used IP cores are listed in
table 3.
Note that the table above lists IP cores used in the full set of planned LEON-XCKU-EX designs. Sev -
eral designs contain a subset of the IP cores in the table.
3.2 Interrupts
The LEON-XCKU-EX example designs use the same interrupt assignment for all configurations. See
the description of the individual cores for how and when the interrupts are raised. All interrupts are
handled by the interrupt controller and forwarded to the processor.
Table 3. Used IP cores
Core Function Vendor Device
AHBCTRL AHB Arbiter & Decoder 0x01 -
APB3CTRL AHB/APB3 Bridge 0x01 0x0A2
APBCTRL AHB/APB Bridge 0x01 0x006
LEON3FT LEON3 SPARC V8 32-bit processor 0x01 0x053
DSU3 LEON3 Debug support unit 0x01 0x004
L3STAT LEON3 Performance counters 0x01 0x098
LEON4 LEON4 SPARC V8 32-bit processor 0x01 0x048
DSU4 LEON4 Debug support unit 0x01 0x049
L4STAT LEON4 Performance counters 0x01 0x047
LEON5 LEON5 SPARC V8 32-bit processor 0x01 0x0BA
DSU5 LEON5 Debug support unit 0x01 0x0BB
L5STAT LEON5 Performance counters 0x01 0x0B9
AHBUART Serial/AHB debug interface 0x01 0x007
AHBJTAG JTAG/AHB debug interface 0x01 0x01C
AHBSTAT AHB failing address register 0x01 0x052
APBUART 8-bit UART with FIFO 0x01 0x00C
GPTIMER Modular timer unit with watchdog 0x01 0x011
IRQMP LEON3 Interrupt controller 0x01 0x00D
GRGPIO General purpose I/O port 0x01 0x01A
L2CACHE Level-2 Cache Controller 0x01 0x04B
Xilinx MIG Xilinx DDR4 MIG - with GRLIB wrapper 0x01 0x090
Table 4. Interrupt assignment
Core Interrupt Comment
AHBSTAT 4 Not included in all EX variants
APBUART 2
GPTIMER 8, 9
GRETH_GBIT 5