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Caen V895 Series Скачать руководство пользователя страница 7

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Title:

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Revision:

User's Manual (MUT)

Mod. V895 16 Channel Leading Edge Discriminator

19/03/09

3

NPO:

Filename:

Number of pages:

Page:

00101/97:V895x.MUTx/03 v895_rev3.doc

25

7

1.2. Block

diagram

Fig. 1.2: Block Diagram

DACs,TEST,

INHIBIT

W LOGIC

VME

INTERFACE

8 bit

DAC

ch.0

8 bit

8 bit

8 bit

ch.1

ch14

ch.15

........................

THRESHOLDS

.................

discr.

INPUTS<0..15>

test

inhibit

ch.0

ch.1

ch.14

ch.15

TEST

VETO

OUTPUTS<0..15> A, B

OR LED

..................

discr.

discr.

discr.

AND WIDTH

OR OUT

Σ

MAJ

8 bit

DAC

MAJ

DAC

DAC

DAC

VME
BUS

«
...
5
6
7
8
9
...
»

Содержание V895 Series

Страница 1: ...Technical Information Manual 19 March 2009 Revision n 3 MOD V895 series 16 CHANNEL LEADING EDGE DISCRIMINATORS NPO 00101 97 V895x MUTx 03...

Страница 2: ...responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any...

Страница 3: ...RS 12 2 4 1 INPUT connectors 12 2 4 2 OUTPUT connectors 12 2 5 OTHER COMPONENTS 13 2 5 1 Displays 13 2 5 2 Switches 13 2 5 3 Jumpers 13 2 6 CHARACTERISTIC OF THE SIGNALS 16 3 VME INTERFACE 17 3 1 ADDR...

Страница 4: ...BLOCK DIAGRAM 7 FIG 2 1 MOD V895 FRONT PANEL 11 FIG 2 2 COMPONENTS LOCATION 14 FIG 2 3 JUMPERS LOCATION 15 FIG 2 4 VETO SIGNAL 16 FIG 3 1 MODULE IDENTIFIER WORDS 19 FIG 4 1 V895 UPDATING AND NON UPDA...

Страница 5: ...ent Sum output generates a current proportional to the input multiplicity i e to the number of channels over threshold at a rate of 1 0 mA per hit 20 A MAJORITY output provides a NIM signal if the num...

Страница 6: ...6 Table 1 1 Versions available for the Model V895 Fig 1 1 Model type label example V895 B 1 A label on the printed board soldering side indicates the module s version see Fig 1 1 2 The version with t...

Страница 7: ...ages Page 00101 97 V895x MUTx 03 v895_rev3 doc 25 7 1 2 Block diagram Fig 1 2 Block Diagram DACs TEST INHIBIT WLOGIC VME INTERFACE 8bit DAC ch 0 8bit 8bit 8bit ch 1 ch14 ch 15 THRESHOLDS discr INPUTS...

Страница 8: ...r requirements Refer to 2 2 Threshold range 1 mV to 255 mV 1 mV step Input Signals Inputs Channels 16 inputs negative polarity DC coupling Input Impedance 50 Reflections 4 for input pulses of 2 ns ris...

Страница 9: ...v895_rev3 doc 25 9 Output Signals Outputs 16 ECL outputs with a fan out of two Outputs Impedance 110 Output Width 5 1 ns to 40 5 ns FWHM Output Rise Fall Time 3 ns Input Output Delay 15 5 1 5 ns Cross...

Страница 10: ...ions 2 1 Packaging The Models V895 and V895 B are housed in a 6U high 1U wide VME unit The Mod V895 is provided with P1 P2 and PAUX connectors The Mod V895 B is provided with P1 P2 connectors NO PAUX...

Страница 11: ...el Leading Edge Discriminator 19 03 09 3 NPO Filename Number of pages Page 00101 97 V895x MUTx 03 v895_rev3 doc 25 11 2 3 Front panel Mod V895 LED 16 CH 16 CH OR MAJ I N 2 0 4 6 3 1 5 7 I N 12 14 10 8...

Страница 12: ...Electrical specifications standard NIM logic signal high impedance 15 ns minimum FWHM leading edge of the VETO signal must precede of at least 8 ns the leading edge of the input and overlap completely...

Страница 13: ...impedance 2 5 Other components 2 5 1 Displays The front panel hosts the following LEDs DTACK Type 1 green LED Function VME selected it lights up during a VME access OR Type 1 green LED Function it li...

Страница 14: ...or OR MAJ SUM Base address bit 23 20 Base address bit 19 16 Base address bit 31 28 Base address bit 27 24 Component side of the board Rotary switches for Base Address selection 0 8 4 C 3 B 1 9 A 2 7 F...

Страница 15: ...Channel Leading Edge Discriminator 19 03 09 3 NPO Filename Number of pages Page 00101 97 V895x MUTx 03 v895_rev3 doc 25 15 Fig 2 3 Jumpers location Updating Non Updating VME P2 connector VME P1 connec...

Страница 16: ...nput and overlap completely the input signal see Fig 2 4 N B the VETO signal doesn t act on TEST input INPUT SIGNAL THRESHOLD T T VETO time T min 8 ns T 0 T Requirements T 15 ns Fig 2 4 Veto signal TE...

Страница 17: ...or Base 284C the same register is accessed Table 3 1 Address Map ADDRESS REGISTER CONTEN T TYPE Base 00 Base 02 Base 04 Base 06 Base 08 Base 0A Base 0C Base 0E Base 10 Base 12 Base 14 Base 16 Base 18...

Страница 18: ...number between 0 and 255 into the register The set value corresponds to the width as follows 255 leads to a 40 ns pulse duration 0 leads to a 5 ns pulse duration with a non linear relation for interm...

Страница 19: ...ess FA FC FE read only Three words located at the Base address FA FC FE of the page are used to identify the module as shown in Fig 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 V e r s i o n M o d u l e...

Страница 20: ...ugh this connector allows to inhibit all channels simultaneously Its leading edge must precede the input signal leading edge by at least 8 ns and overlap completely the input signal It doesn t act on...

Страница 21: ...ts output width for channels 0 to 7 Base 42 sets output width for channels 8 to 15 Valid data for the 8 bit registers are 0 leads to 5 ns 255 leads to 40 ns with a non linear relation for intermediate...

Страница 22: ...f pages Page 00101 97 V895x MUTx 03 v895_rev3 doc 25 22 T 5 40 ns programmable T min 7ns Double Pulse Resolution updating 12ns Double Pulse Resolution non updating Fig 4 1 V895 Updating and Non Updati...

Страница 23: ...urrent Sum signal The Current Sum output connector provides a current proportional to the input signal multiplicity i e to the number of channels over threshold at a rate of 1 0 mA per hit 50 mV per h...

Страница 24: ...to an External position by means of an internal Jumper see Fig 2 3 Internal With the jumper on the Internal position Majority output provides an active signal if the number of the active channels of t...

Страница 25: ...umber of Module s active Channels 5 4 3 Majority Output ACTIVE 5 MAJLEV NON Active 4 MAJLEV ACTIVE 5 4 3 MAJLEV Fig 4 3 Example of three daisy chained V895 12 mA 2 3 1 Maj State EXT Maj State INT 50 o...

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