CAEN
Electronic Instrumentation
UM5175
–
V2495/VX2495 User Manual rev. 1
12
3.1
USB Interface
The V2495 is equipped with a USB2.0 interface. The USB physical layer is managed by a high-speed (480 Mb/s)
transceiver controlled by the Main FPGA.
3.2
VME Interface
The P1 and P2 are the standard VME connectors both interfaced with the Main FPGA.
3.3
Main FPGA
The MFPGA (Altera Cyclone V E) manages the VME and USB interfaces and the connection with the UFPGA through a
proprietary 16-bit@50 MHz local bus. The MFPGA has a dedicated external flash memory for configuration purposes. It
also pilots the flash memories dedicated to loading the firmware on the UFPGA and on the GDG.
3.4
User FPGA
The User FPGA (Altera Cyclone V GX) manages the I/O peripherals (A/D, B/E, G, C/F ports) and communicates with the
GDG. A dedicated external flash memory can store a set of firmware images to be loaded on the User FPGA. A
dedicated JTAG connector allows to program the UFP
GA “on
-the-
fly” for fast firmware prototyping and debugging.
3.5
Gate and Delay Generator
The V2495 hosts a Gate and Delay Generator (see
able to provide up to 32 gated and delayed signals (“delayed
signals”) triggered by 32 inputs (“start signals”). The gate width and de
lay value are user programmable. The GDG is an
external component implemented in a Xilinx Spartan-6 FPGA. It is connected through a serial bus (SPI) to the User
FPGA for gate and delay register programming (refer to Sect.
for detailed information). The
GDG configuration is stored in a dedicated flash memory. The GDG firmware cannot be modified by the user.
User FPGA
Gate and Delay
Generator
32
32
Start signals
Delayed signals
Start[i]
Delayed[i]
Td
Tg
Fig. 3.2:
The UFPGA and GDG interface.
3.6
Clock Distribution
Each FPGA receives the same 50-MHz system clock generated by a common on-board oscillator.
