Trigger Management
When opera ng the waveform recording firmware, all board channels share the same trigger (board com-
mon trigger), so they acquire an event simultaneously and in the same way (determined number of samples
according to buffer organiza on and custom size se ngs, as well as posi on with respect to the trigger de-
fined by the post-trigger).
TRG IN
Enable Mask
x4
4
4
TRIGGER
SW TRG
GPO
LOCAL TRG
D
Q
SCLK
Acquisition
Logic
Memory
Buffers
ADC
Digital
Thresholds
4
Local Bus
Interface
Mother Board
x2 mezzanines
x2 channels
Fig. 7.13:
Block diagram of Trigger management.
•
So ware Trigger
•
External Trigger
•
Self-trigger
•
Coincidences
•
TRG-IN as Gate
Software Trigger
So ware triggers are internally produced via so ware command (write access at register address 0x8108)
through USB or Op cal Link.
External Trigger
A TTL or NIM external signal can be provided to the front panel TRG-IN connector (configurable at register
address 0x811C). If the external trigger is not synchronized with the internal clock, a 1-clock period ji er
occurs.
38
UM3247 - N6724 User Manual rev. 10
