DAMC-FMC20 User’s Manual
13
Distribution of TCLKB to main FPGA global clock and RTM (multiplexed
with TCLKA);
Distribution of RTM clock to main FPGA global clock and transceiver FPGA
(MGT clock);
Two clock sources for first MGT tile on transceiver FPGA: PCIe clock and
FMC clock;
Two clock sources for second MGT tile on transceiver FPGA: FMC clock and
(as a placement option) RTM clock or 125 MHz fixed LVDS clock;
200 MHz LVDS clock source for each FPGA as global clock.
