CMM-9304-V2.1
Bluetooth 4.2 / 5.0 compatible module
SPEC No.
CMM-9304-V2.1
BLE module
Revision
2.8
State
2017-11-13
C-MAX printed
2017-11-13
Version
English
Page
5 of 11
C-MAX
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RDY at '0'
buffer is not ready and byte cannot be written/read. SPI master has to
wait until
RDY is at '1'.
After asserting CSN and before sending first byte SPI Master
checks if RDY is at '1'. This check shall be done at least T_RDY (100ns) after
asserting CSN. If RDY is at '1' SPI transaction can start, if RDY is at '0' SPI
master has to wait until RDY is at '1'.
An example of write transaction using RDY as a flow control during transaction is shows in Figure 1.
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Figure 1: SPI Slave write transaction with active flow control by means of RDY.
2.3
Flow Control using Byte count in Status Byte STS2
A Master with DMA, using the status byte STS2, can run an SPI transaction without interruptions. In
this case SPI Master can ignore RDY during the SPI transaction and use instead the status byte STS2
to determine the maximum length of the SPI transaction. Once maximum length of SPI transaction is
known (from STS2), the SPI Master can configure the DMA to realize the rest of the SPI transaction.
After transmitting the given number of bytes (less than or equal to maximum length determined from
STS2) SPI transaction shall be finished by de-asserting CSN. A new SPI transaction shall start by
asserting CSN and reading status bytes to determine maximum length of this new transaction.
Examples of transactions ignoring RDY are shown in Figure 2 and in Figure 3.
Figure 2: SPI Slave Write Transaction.
Figure 3: SPI Slave Read Transaction.