BVM PMCDIO64, Руководство пользователя

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PMCDIO64
Copyright

2000 BVM Ltd.
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7.3.4 Direction Register
The 8-bit read/write Direction Register where each bit corresponds to a group of 8 I/O bits. If the
corresponding bit is set to 1 the bit is enabled as an output otherwise it is enabled as an input.
7 6 5 4 3 2 1 0
IO63-56 IO55-48 IO47-40 IO39-32 IO31-24 IO23-16 IO15-8 IO7-0
7.3.5 Function Register
The 8-bit read only Function Register contains the low byte of the PCI Subsystem Device ID - in this
case 65 (hexadecimal). This can be used to determine the type of board fitted from the PMCDIO and
PMCCTR range.
7.3.6 Status & Control Register
The 16-bit read/write Status & Control Register is used to control a number of the module functions as
described below. Reserved bits (RSVD) read as zero and should be written as zero for future
compatibility.
7 6 5 4 3 2 1 0
WDGST IWDEN RSVD GOPEN WINEN RSVD RSVD RSVD
15 14 13 12 11 10 9 8
IOCST IOCEN OUTHLD INLOCK RSVD RSVD RSVD RSVD
7.3.6.1 Watchdog Interrupt Enable (Bit 3: WINEN)
When set to 1 this bit enables the generation of a PCI Interrupt if an enabled internal watchdog times
out - see section "7.3.6.3 Internal Watchdog Enable (Bit 6: IWDEN) (below)". If clear no PCI Interrupt
will be generated.
7.3.6.2 Global Output Enable (Bit 4: GOPEN)
When set to 1 signals selected as outputs are enabled. If clear signals selected as outputs are
disabled. Input signals are unaffected.
7.3.6.3 Internal Watchdog Enable (Bit 6: IWDEN)
When set to 1 the internal watchdog function is enabled and if the watchdog times-out then the
outputs will be disabled. If clear the state of the watchdog is ignored.
7.3.6.4 Watchdog Status (Bit 7: WDGST)
When set to 1 this bit indicates an enabled internal watchdog has timed-out - see section "7.3.6.3
Internal Watchdog Enable (Bit 6: IWDEN) (above)". Once set this bit cannot be cleared.
7.3.6.5 Input Lock (Bit 12: INLOCK)
When set to 1 the Input Register will be locked and will not be updated when the input signals change.
If clear the Input Register will reflect the state of the input signals.
7.3.6.6 Output Hold (Bit 13: OUTHLD)
When set to 1 then signals selected as outputs will not be updated from the Output Register, but the
Output Register can still be written. When clear then the signals selected as outputs will reflect the
state of the Output Register
7.3.6.7 Interrupt On Change-of-State Enable (Bit 14: IOCEN)
When set to 1 a PCI interrupt will be generated when signals selected as inputs change state. When
clear no PCI interrupt will be generated on input change-of-state. Note that when change-of-state
mode is enabled that the Input Register will be locked and will not be updated until the mode is
disabled.
7.3.6.8 Interrupt On Change-of-State Status (Bit 15: IOCST)
This bit is set to 1 if any change flags are set after Interrupt On Change-of-State has been enabled.
Writing a 1 clears all change flags.