Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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The ROM can also be accessed by a local bus master by driving the XCSROM# signal on the CPLD
(prototyping pad PC7) in conjunction with the local bus address, data, control and bus arbitration signals.
Note: When a 3.3V device is used in the ROM socket, please make sure it has 5V-tolerant I/O.
3.7 Test Headers
Six logic analyzer headers are implemented with the standard 0.1”, 2x10 Hewlett Packard configuration.
These headers can be used for signal probing or prototype area expansion. All PCI 9052 local bus,
configuration and status signals are well arranged within these headers. Headers LAH1 and LAH2
contain local bus address signals. Headers LAH3 and LAH4 contain local bus data signals (or multiplexed
address/data signals in the multiplexed mode). Headers LAH5 and LAH6 contain local bus control and
status signals. Designers can use these
headers to connect to a standard prototyping board for additional
prototyping. The headers do not provide any power source; therefore, VCC must be connected separately
for prototyping daughter-boards.
3.8 CPLD Functionality
The PCI 9052RDK-LITE includes an Altera EPM3064ATC100 CPLD (U5). This CPLD is used to generate
various control signals for the RDK board. While not required to interface the PCI 9052 to the ISA bus,
using a small CPLD makes the RDK as flexible as possible as a development platform. It performs the
following functions:
•
Clock division to generate 16 MHz and 8 MHz signals for LCLK
•
Memory strobe generation
•
ORing of multiple ISA IRQ lines to generate a single interrupt, minimizing the number of jumpers
that would be required to route multiple IRQ lines to the PCI 9052 LINTi1 local interrupt pin
•
Logic to allow optional local bus masters to access the on-board memory
The rest of the device (over 50%) is available to the user for prototyping purposes. There are 15 spare
pins on the CPLD connected to prototyping pads PC1 and PC8-PC21 for linking to other components or
local bus signals.
The CPLD can easily be reprogrammed via the JTAG ISP header J7. The design is provided on the HDK
CD-ROM in the Altera
®
MAX+PLUS
®
II graphic design file (.gdf) format. The easiest way to customize
the PLD design is to import the .gdf file into the MAX+PLUS II software and modify the design. The
MAX+PLUS II Baseline version is available free of charge from Altera. Please refer to the Altera website
(www.altera.com) or contact an Altera representative for further details.
For a graphical representation of the program contained within the CPLD, refer to the schematics
contained later in this manual.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
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© 2004 PLX Technology, Inc. All rights reserved.