Broadcom PLX PCI 9052RDK-LITE, Справочник по аппаратуре

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2. PCI 9052 Overview
2.1 PCI 9052 Introduction
The PLX PCI 9052 provides a compact, high-performance PCI bus target (slave) interface for adapter
boards. It is designed to connect a wide variety of local bus designs to the PCI bus and allow them to
achieve high data rate burst transfers on the PCI bus.
The PCI 9052 can be programmed to connect directly to an 8- or 16-bit local ISA bus as well as to 8-, 16-,
or 32-bit multiplexed or non-multiplexed local busses.
The PCI 9052 contains read and write FIFOs to speed-match a 32-bit wide, 33 MHz PCI bus to a local
bus, which may be a different width and/or speed. Up to five local address spaces and up to four local
chip selects are supported.
2.2 PCI 9052 Feature Set
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PCI v2.1 compliance: The PCI 9052 is compliant with PCI Specification v2.1, supporting low
cost slave adapters. It facilitates the simple conversion of ISA adapters to PCI target adapters.
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Direct slave (Target) data transfer mode. The PCI 9052 supports burst memory-mapped and
single-cycle I/O mapped accesses from the PCI bus to the local bus. The read and write FIFOs
enable high performance bursting on the local and PCI bus. When the PCI bus is bursting, the
local bus can either perform burst accesses or multiple single-cycle accesses.
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Interrupt generator. The PCI 9052 can generate a PCI interrupt from two local bus interrupt
inputs or by software writing to an internal register bit.
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Clock. The PCI 9052 local bus runs from a local TTL clock and generates necessary internal
clocks. This clock runs asynchronously to the PCI clock allowing the local bus to be run at an
independent rate. The buffered PCI bus clock output (BCLKO) may be connected to the local
bus clock (LCLK) input through a 50-Ohm series resistor if desired.
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Programmable local bus configurations. The PCI 9052 supports 8-, 16-, or 32-bit local buses,
which may be multiplexed or non–multiplexed. The PCI 9052 has four byte enables (LBE[3:0]#),
26 address lines (LA[27:2]) and up to 32 data lines (LAD[31:0]).
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Read ahead mode. The PCI 9052 supports Read Ahead mode, where pre-fetched data can be
read from the PCI 9052 internal FIFO instead of from the local bus. Addresses must be
sequential and 32-bit aligned (next address = current a4).
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Bus drivers. All control, address and data signals generated by the PCI 9052 drive the PCI and
local buses, without the need for external drivers.
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Serial EEPROM interface. The PCI 9052 contains a serial EEPROM interface, used to load
configuration information. This is useful for loading information unique to a particular adapter
(such as Device ID, Vendor ID, and local bus configuration information).
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Four local chip selects. The PCI 9052 provides up to four local bus chip selects (CS[3:0]#).
The base address and range of each are independently programmable from the serial EEPROM
or host.
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Five local address spaces. The base address, range, bus width and timing of each local
address space are independently programmable from the serial EEPROM or host.
•
Big/Little Endian byte swapping. The PCI 9052 supports local bus Big and Little Endian byte
ordering. The PCI 9052 also supports Big Endian byte lane mode to redirect the current
word/byte lane during 16- or 8-bit local bus operation.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved . 3