BCM1250/BCM1125/BCM1125H
User Manual
10/21/02
B r o a d c o m C o r p o r a t i o n
Page
300
Section 9: Ethernet MACs
Document
1250_1125-UM100CB-R
In this mode flow control is provided in each direction. Transmit flow control is input on the TX_FC pin, when
this is asserted the interface will stop sending data (and drive the data not valid control code) two rising clock
edges later. The part will assert the RX_FC pin as a receive flow control output if (a) the CPU sets the force
flow control configuration bit; (b) the number of descriptors on a receive channel falls below the low watermark
and automatic flow control is enabled for that channel; or (c) there are less than four 64 bit words left free in
the receive FIFO. If the device the other end of the link honours the flow control request within a few clock times
data will never be lost on the link.
In this mode a transmit FIFO underflow during transmission of a packet causes bubbles to be inserted in the
data stream (the data not valid code will appear during a packet) but transmission will not be aborted. (In all
other modes a transmit FIFO underrun causes the packet to be aborted).
R
ESTRICTIONS
W
HEN
R
ESETTING
THE
I
NTERFACE
The MAC and Packet Fifo logic is automatically reset when the part is reset. However, on BCM1250s prior to
PERIPH_REV3, correct reset of the logic requires that there be a few rising edges on REFCLK01 (for MACs
E0 and E1) and REFCLK2 (for MAC E2) before software releases the interface from reset. This is not normally
a problem since the clocks will be free running. If the clocks are not provided then the first access to the
registers for the corresponding interface will place the ZBbus in an UNDEFINED state. If an interface is not
used there are two options: (1) ensure software never accesses the unused interface registers; (2) provide
some edges on the reference clock before software can access the registers. Clearly (2) is preferable, since
otherwise a bug in the software (or even a debugger collecting the system state) could cause a hang that would
be hard to track down. There is no need to provide a periodic clock. One possible solution would be to connect
the unused REFCLK input to the boot ROM chip select (or SCL if the system boots from SMBus) since this is
guarenteed to toggle when the part comes out of reset (before any instructions run the SB-1 will have fetched
16 bytes from the boot ROM, thus there will be 4 (for a 32 bit ROM) or 16 (for an 8 bit ROM) edges on the
REFCLK even in the unlikey case where the first instruction accesses the MAC registers).
The interface can also be reset by software. Again, for parts prior to PERIPH_REV3 the clock needs to be
running for correct operation (note that if the clock was running during the chip reset and the MAC is not being
used then it is safe to perform a software reset without a clock). This can be done by setting the (self-clearing)
p_reset bit in the
mac_enable
register. After this bit has been written with a 1, the software should delay for
at least six times the clock period of the receive clock then write the bit with a 1 again. Following the second
write the interface will be fully reset. (If this sequence is not followed the interface will reset but it is possible
for a junk packet to be received when the receiver is enabled again). Before software resets the MAC (or a
DMA channel) it should ensure that there is no outstanding DMA activity (failure to do this can cause resources
to be lost between the MAC and ZBbus and can degrade performance). The DMA should be stopped by
clearing the descriptor count by writing the complement of the current count into the count register (the
hardware will add this value and discard the carry so the count will become zero), then reading any of the DMA
registers, then waiting for twice the transmission time of a maximum length packet (this ensures any in-
progress transmission or reception has completed). Once the DMA has stopped the reset can be safely written.
Start of Packet, 2 Bytes Valid
101
End of Packet, 2 Bytes Valid
110
Middle of Packet, 2 Bytes Valid
111
Table 175: Codes for 16-Bit Encoded Bypass Mode
TXC/RXC[2:0]
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