Broadcast Electronics FX-50, Инструкция по эксплуатации

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F. VCO Activity Monitor
G. Audio Processing Circuits
H. Pre-modulation Control Circuit
I. Voltage Regulator Circuits
9.5.1 REFERENCE DIVIDER CIRCUIT.
This divider circuit provides an accurate and stable reference frequency for input to a comparator circuit. A 10
MHz signal from crystal oscillator Y1 is input to divide-by-five counter U1B to produce 2 MHz. These two
frequencies are available at TP1 through programmable jumper J3.
The 2 MHz signal from U1B is input to divide-by-two counter U1A to produce 1 MHz. Logic circuits U2, U3,
and U4A further divide the 1 MHz signal by 250 to provide 4 kHz to one shot U5. The 4 kHz signal at the QA
output of U5 is applied to programmable frequency synthesizer and comparator U9.
9.5.2 REFERENCE OSCILLATOR ACTIVITY MONITOR.
This circuit provides a visual indication of the reference divider circuit output. When the 4 kHz signal is present,
the QB output of U5 will go HIGH which biases LED driver transistor Q1 ON to illuminate indicator DS2.
9.5.3 RF SAMPLE DIVIDER CIRCUIT.
This divider circuit provides an RF sample frequency for input to the comparator circuit. An RF sample from the
modulated oscillator is input to transformer T1 to reduce ground loop interference. The output of T1 is coupled
to a low-pass filter consisting of capacitors C15, C16, and inductor L3 which eliminates any harmonics.
The sinusoidal output signal from the low-pass filter is applied to the input of counter U8. U8 will divide the
sample frequency by 20 and output a digital signal to U9.
9.5.4 COMPARATOR CIRCUIT.
This circuit compares the signals from both the reference divider and RF sample divider circuits and generates an
error signal when a difference exists. Logic circuit U9 is a programmable frequency synthesizer and comparator
which will internally divide the 4 kHz signal at the OSC input to provide a frequency of 500 Hz.
When binary switches S1, S2, and S3 are preset for the appropriate carrier frequency, U9 will divide the RF
sample signal at the F input to provide 500 Hz at the FV output which is applied to one shot U12. If an error
exists, output FV will vary above or below 500 Hz. This signal and the 500 Hz from the reference division are
internally compared for phase and frequency variations.
When the carrier frequency and reference frequency are equal and in phase, the PD output of U9 will be steady
state at approxi2.5 volts. If the carrier leads or is greater than the reference frequency, the output will
pulse LOW. If the carrier lags or is less than the reference frequency, the output will pulse HIGH. These output
pulses will vary in width directly in proportion to the degree of phase error. The pulses are applied to U11B.
Normally, the LD output of U9 will be a logic HIGH for a locked condition. If an unlocked condition exists, the
output will pulse LOW. This output is applied to the D input of lock/ unlock sensor U4B. With the signal from
the FV output of U9, the QA output of one shot U12 will provide a clock pulse to U4B which leads or lags the
signal at the D input depending on the phase error direction.
9.5.5 LOOP FILTER CONTROL CIRCUIT.
The loop filter control circuit increases/decreases the voltage controlled oscillator (VCO) center frequency to
maintain accuracy. U10B biases integrator/amplifier U11B at 2.5V to provide a voltage gain of 11 for any
differential voltage within the range of the bias. The output of U11B is applied to the metering circuit board for
display.