16
its period setting comes ending of every 1, 2, 10, 20, 110 or 220 seconds
( Please reference to the selection table of JP8 for WDT Time-Out period
setting ). If the Refresh cycle does not
active before WDT period cycle, the on board WDT architecture will
issue a Reset or NMI cycle to the system.
The Watch-Dog Timer is controlled by two I/O ports.
443H
I/O Read The Enable cycle.
443H
I/O Read The Refresh cycle.
043H
I/O Read
The Disable cycle.
The following sample programs showing how to Enable, Disable and
Refresh the Watch-dog timer:
WDT_EN_RF
EQU
0433H
WDT_DIS
EQU 0043H
WT_Enable
PUSH
AX
;
keep
AX
DX
PUSH
DX
MOV
DX,WDT_EN_RF ; enable the watch-dog timer
IN
AL,DX
POP
DX
;
get
back
AX,
DX
POP
AX
RET
WT_Refresh
PUSH
AX
; keep AX, DX
PUSH
DX
MOV
DX,WDT_ET_RF
; refresh the watch-dog timer
IN
AL,DX
POP
DX
;
get
back
AX,
DX
POP
AX
RET
WT_DISABLE
PUSH
AX
PUSH
DX
MOV
DX,WDT_DIS
; disable the watch-dog timer
IN
AL,DX
POP
DX
;
get
back
AX,
DX
POP AX
RET
