11
CN10: LVDS Connector
PIN
Description
PIN
Description
1
A_DATA0-/DVI_TLC-
2
B_DATA0-
3
/
4
5
A_DATA1-/DVI_TDC0-
6
B_DATA1-
7
/D
8
9
A_DATA2-/DVI_TDC1-
10
B_DATA2-
11
/D
12
13
A_DATA3-
14
B_DATA3-
15
16
17
GND
18
GND
19
A_CLK-/DVI_TDC2-
20
B_CLK-
21
A_CLK+/D
22
B_CLK+
23
LVDS_VCC
24
LVDS_VCC
25
+5V(DVI)
26
+5V(DVI)
27
DVI_CLK
28
LDDC_CLKL
31
DVI_DATA
30
LDDC_DATA_L
Signal
Type
Description
LDDC_CLKL
I/O
EDID support for flat panel display
LDDC_DATAL
I/O
EDID support for flat panel display
/-
O
DVI Clock Output: These pins provide the differential
clock outputs to the DVI interface corresponding a data
on TDC(0:2) outputs
D/-
O
DVI Data Channel 0 Output:
These pins provide the
DVI differential output for data channel 0 (Blue)
D/-
O
DVI Data Channel 1 Output:
These pins provide the
DVI differential output for data channel 1 (Green)
D/-
O
DVI Data Channel 2 Output:
These pins provide the
DVI differential output for data channel 2 (Red)
DVI_CLK
DVI_DATA
I/O Serial Port (SMBus) Clock and Data. The SPCLK
signals are the clocks for serial data transfer. The SPD
signals are the data signals used for serial data
transfer. SPCLK1/SPD1 is typically used for DVI
monitor communications.
Содержание HS-2622
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