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5.6 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
the access to the system memory resources, such as DRAM and the
external cache. It also coordinates the communications between the
conventional ISA and PCI buses. It must be stated that these items
should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You must consider making any changes only if you discover that the
data has been lost while using your system.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Clock/Drive Control
[Press Enter]
Item Help
AGP & P2P Bridge Control
[Press Enter]
CPU & PCI Bus Control
[Press Enter]
Memory
Hole
[Disabled]
System BIOS Cacheable
[Enabled]
Video RAM Cacheable
[Disabled]
Init Display First
[PCI Slot]
↑↓←
→
: Select Item
+/-/PU/PD: Value
F10: Save
Esc: Quit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
Current FSB Frequency
100MHz
Item Help
Current DRAM Frequency
200MHz
DRAM Timing
[Auto By SPD]
X SDRAM CAS Latency [DDR/DDR
2.5/4
X Bank Interleave
Disabled
X Precharge to Active(Trp)
4T
X Active to Precharge(Tras)
07T
X Active to CMD(Trcd)
4T
X REF to ACT/REF(Trfc)
25T
X ACT(0) to ACT(1) (TRRD)
3T
Read to Precharge (Trtp)
[2T]
Write to Read CMD (Twtr)
[1T/2T]
Write Recovery Time (Twr)
[4T]
DRAM Command Rate
[2T Command]
RDSAIT
mode
[Auto]
X RDSAIT selection
03
↑↓←
→
: Select Item
+/-/PU/PD: Value
F10: Save
Esc: Quit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Содержание HS-2613
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