M
M
M
o
o
o
t
t
t
h
h
h
e
e
e
r
r
r
b
b
b
o
o
o
a
a
a
r
r
r
d
d
d
D
D
D
e
e
e
s
s
s
c
c
c
r
r
r
i
i
i
p
p
p
t
t
t
i
i
i
o
o
o
n
n
n
29
Note: Because the overclock, overvoltage, and hardware monitor
features are controlled by several separate chipset,
[ WarpSpeeder™ ] divide these features to separate panels. If one
chipset is not on board, the correlative button in Main panel will be
disabled, but will not interfere other panels’ functions. This property
can make [ WarpSpeeder™ ] utility more robust.
Содержание P4 TGV
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