Chapter 2
BIOS Setup
2-14
DRAM Timing Selectable
The default is By SPD.
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing.
The Choices: 1.5
(default), 2, 2.5, 3.
Active to Precharge Delay
This item controls the number of DRAM clocks to activate the precharge
delay.
The Choices: 7
(default), 6, 5.
DRAM RAS# to CAS# Delay
This field let you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Fast
gives faster performance; and slow gives more stable performance. This
field applies only when synchronous DRAM is installed in the system.
The Choices: 3
(default), 2.
DRAM RAS# Precharge
If an insufficient number of cycle is allowed for RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete, and the
DRAM may fail to retain data. Fast gives faster performance; and Slow
gives more stable performance. This field applies only when synchronous
DRAM is installed in the system.
The Choices: 3
(default), 2.
DRAM Data Integrity Mode
This item select supported ECC or Non-ECC for DRAM.
The Choices: Non-ECC
(default), ECC.
Memory Frequency For
The default is
Auto
.
Dram Read Thermal Mgmt
The Intel 845 Chipset MCH provides Memory Thermal Management
functionality. It increases the system reliability by decreasing thermal
stress on system memory and on the Intel 845 Chipset MCH.
The Choices: Disabled
(default), Enabled.
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