Motherboard Manual
46
6.3 AMI
BIOS
P
OST
C
ODE
Code Description
10
PEI Core is started
11
Pre-memory CPU initialization is started
15
Pre-memory North Bridge initialization is started
19
Pre-memory South Bridge initialization is started
2B
Memory initialization. Serial Presence Detect (SPD) data reading
2C
Memory initialization. Memory presence detection
2D
Memory initialization. Programming memory timing information
2E
Memory initialization. Configuring memory
2F
Memory initialization (other).
31 Memory
Installed
32
CPU post-memory initialization is started
33
CPU post-memory initialization. Cache initialization
34
CPU post-memory initialization. Application Processor(s) (AP) initialization
35
CPU post-memory initialization. Boot Strap Processor (BSP) selection
36
CPU post-memory initialization. System Management Mode (SMM) initialization
37
Post-Memory North Bridge initialization is started
3B
Post-Memory North Bridge initialization (North Bridge module specific)
4F
DXE IPL is started
60
DXE Core is started
F0
Recovery condition triggered by firmware (Auto recovery)
F1
Recovery condition triggered by user (Forced recovery)
F2
Recovery process started
F3
Recovery firmware image is found
F4
Recovery firmware image is loaded
E0
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
E1
S3 Boot Script execution
E2 Video
repost
E3
OS S3 wake vector call
60
DXE Core is started
61 NVRAM
initialization
62
Installation of the South Bridge Runtime Services
63
CPU DXE initialization is started
68
PCI host bridge initialization
69
North Bridge DXE initialization is started
6A
North Bridge DXE SMM initialization is started
70
South Bridge DXE initialization is started
71
South Bridge DXE SMM initialization is started
72
South Bridge devices initialization
78
South Bridge DXE Initialization (South Bridge module specific)
79
ACPI module initialization
90
Boot Device Selection (BDS) phase is started
91
Driver connecting is started
92
PCI Bus initialization is started
93
PCI Bus Hot Plug Controller Initialization
94
PCI Bus Enumeration
95
PCI Bus Request Resources
96
PCI Bus Assign Resources
97
Console Output devices connect
98
Console input devices connect
