BESTEK NSP-2C30, Руководство пользователя

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PCI Subsystem Settings
PERR# Generation
Disable to suppress the PCI bridge data parity error generation capability
SERR# Generation
Disable to suppress the PCI bridge system error generation capability.
Above 4G Decoding
This is to enable/disable memory mapped I/O for a 64 ‐ bit PCIe device to 4GB or greater address space,
because the primary VGA card should always be mapped below 4GB address. However, please keep this
setting disabled if system appears to be unstable. Clear CMOS once BIOS setup menu is no longer available.
SR ‐ IOV Support
This is to enable/disable single root I/O virtualization (SR ‐ IOV) interface. SR ‐ IOV allows a device, such as a
network adapter, to separate access to its resources among various PCIe hardware functions.
PCI ‐ Express Settings
Relaxed Ordering
Enables or disables PCIe device relaxed ordering of PCI Express traffic through switches and the Root Complex.
Extended Tag
This is to enable or disable Extended Tag. If enabled allows device to use 8 ‐ bit tag field in the Requester
Transaction ID field. If disabled, only 5 bits may be used, limiting the maximum number of outstanding
Requests per Function to 32.
No Snoop
This is to enable or disable the PCIe device No Snoop attribute of PCI Express traffic Refer to the PCI Express
1.0 specification.
Maximum Payload
This is to set the maximum data payload size that a PCI Express device may transmit within a Transaction Layer
Packet from: Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, or 4096 Bytes.
Extended Synch
Enabling this setting allows generation of extended synchronization patterns, which may help to allow logic
analyzers to achieve symbol lock before the link changes power states and resumes communication.
GPIO Configuration
GPIO Expander Configuration
This is to control GPIO mode of GPIO of GPIO Expander and PCH, as Input or Output, and configure the output
as high/low if set to Output.