beneq Lumineq EL320.256-FD6, Руководство по эксплуатации

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Operation Manual
EL320.256-FD6 Display
Beneq Oy
Olarinluoma 9 Tel. +358 9 7599 530 VAT ID FI19563372
FI-02200 Espoo Fax +358 9 7599 5310 www.beneq.com
Finland lumineq@beneq.com www.lumineq.com
Date: February 13, 2017 Document number: ED000814C Page | 6
Pins Signal Symbol Description
4 Low Power _LOWPOW If pulled LOW, the display is in Low Power
Mode. The display has its normal brightness if
HIGH or left disconnected. See page 6.
Pinstrip PS1
1 NC No connection.
2 Two-bit
parallel
DCONFIG The video data is input two pixels per video
clock using VID and TVID if jumper is set.
3 Low Power _LP Low Power Mode is selected when jumper is
set. This function overrules the _LOWPOW
control input.
4 SELFTEST When set, video data input in VID and TVID is
displayed asynchronously.
3.3 Connectors
Table 2. Connectors
J1 16-pin header ODU 511.066.003.016 or eq.
Mating ODU 517.065.003.016 or eq.
J2 4-pin header Hirose DF1–4P–2.5 DSA or eq.
Mating Hirose DF1–4S–2.5 R 24 or eq.
Protector Hirose DF1–4A 1.33
3.4 Control basics
The TFEL panel has 320 transparent column electrodes crossing 256 row electrodes in an X-Y
fashion. Light is emitted when an AC voltage is applied at a row-column intersection. The
display operation is based on the symmetric, line-at-a-time data addressing scheme, which is
synchronized by the external VS, HS, and video clock input signals. The signal inputs are
HCT-compatible with 100 Ω series resistors.
3.5 Power input
The input voltages needed are the +5 V input (V
cc1
) for the logic and the +11 V… +30 V input
(V
cc2
) for the DC/DC converter generating all internal high voltages.