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Operation Manual
EL320.240-FA3 Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI19563372
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: February 13, 2017
Document number: ED000813B
Page | 12
3.5.1
Video mode selection
Inputs LUM0 and LUM1 must be set to attain the desired video mode as shown in the
following table.
LUM0 and
LUM1 = 1?
V/Q
input
DE
input
Mode
name
Mode description
(refer to video mode timing for details)
No
0
Active
AMLCD,
QVGA
AMLCD timing. DE determines the
horizontal location of data.
No
0
0
AMLCD,
QVGA,
Fixed
AMLCD timing. Horizontal start of valid data
is a predetermined number of VCLKs from
HS.
No
1
Active
AMLCD,
VGA
AMLCD timing. Displays the upper left
quadrant of a VGA (640x480) input signal
with DE determining the horizontal location
of data.
No
1
0
AMLCD,
VGA,
Fixed
AMLCD timing. Displays the upper left
quadrant of a VGA (640x480) input signal
with the horizontal start of valid data
predetermined.
No
X
1
SGD
SGD timing. Horizontal start of valid data is
the first VCLK after HS.
Yes
X
X
Self test Displays various patterns at the maximum
refresh rate regardless of video input data.
Useful for verifying display functionality.
Note:
1) DE is considered active if more than 8 logic transitions are detected.
2) SGD mode is similar to that of the Lumineq EL320.240.36 and EL320.240-HB displays, but
with required changes to the video data content to represent color.
3) The AMLCD modes are compatible with those found on the following QVGA displays though
the video data content of 4 bits/pixel is a subset of the typical 18 bits/pixel: Sharp
LQ057Q3DC12, Sharp LQ057Q3DC02, Kyocera TCG057QV1AC.