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Plexus 9000 Planning and Engineering Guide Front System Processor Timing Module
Section 130-120-200 Issue 3, April 23, 2004
Telica, Inc. 5-25
5.2
Front System Processor Timing Module
5.2.1 Scope .................................................................................................................. 5-25
5.2.2 Functional Description ....................................................................................... 5-25
5.2.2.1 Improvements ....................................................................................5-26
5.2.2.2 General Mechanical Representation..................................................5-26
5.2.2.3 Front Panel ........................................................................................ 5-28
5.2.3 Theory of Operation ...........................................................................................5-29
5.2.3.1 Power................................................................................................. 5-29
5.2.3.2 Timing Section .................................................................................. 5-30
5.2.3.3 Processor Section ..............................................................................5-31
5.2.3.4 Redundancy Control..........................................................................5-35
5.2.4 Specifications .....................................................................................................5-36
5.2.1 Scope
This section describes the front System Processor Timing (SP/TMG)
module, which will be referred to as System Processor or SP in this
document. This section explains the module functions, LED indicators,
and connector interfaces.
The CLEI codes of the modules are as follows:
Part Numbers CLEI Codes Comments
89-0366-A BAC7X40JAA
89-0366-B BAC7X40JAB
Note: Shaded part numbers have been “manufacture discontinued,” but
are still supported. The SP-2 or SP-3 modules can be used instead.
5.2.2 Functional Description
Two SPs, comprised of a front and a rear circuit module, are located near
the center of the shelf (slots 9 and 13) and provide full 1+1 redundancy for
critical processing resources for true non-stop operation.
The SPs hold the internal Stratum 3 timing sources. Central office BITS
(Building Integrated Timing Supply) timing is brought into the rear of the
Plexus 9000 via two independent connections located on the rear Switch
Fabric (SF) modules. The timing (TMG) section provides multiplexing
control for routing each of the input clock signals to the individual IOMs
in the chassis. It also provides control circuitry for selecting the master,
supporting failover from the master to the secondary, and generating
alarms when failures on the input clock lines occur.