Beckhoff KL6781, Документация

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Access from the user program
KL6781 20 Version: 2.0.0
Key
Bit Name Description
SW.15 ... SW8 IL7 ... IL0
(InLength)
1
dec
...
22
dec
Number of input bytes available for transfer from the terminal
to the controller.
SW.7 Reg (RegAccess) 0
bin
Acknowledgment for process data mode
SW.6 ... SW.4 - 0 reserved
SW.3 BUF_F 1
bin
The reception FIFO is full. All further incoming data will be
lost!
SW.2 IA
(InitAccepted bit) 1
bin
Initialization was completed by the terminal.
0
bin
The terminal is ready again for serial data exchange.
SW.1 RR
(ReceiveRequest) toggle Via a change of state of this bit the terminal notifies the
controller that the DataIn bytes contain the number of bytes
indicated via the IL bits. The controller has to acknowledge
receipt of the data in the control byte via a change of state of
bit
CW.1 [
}
19] (RA). Only then new data can be transferred
from the terminal to the controller.
SW.0 TA
(TransmitAccepted) toggle The terminal acknowledges receipt of data by changing the
state of this bit. Only then new data can be transferred from
the terminal to the controller
Register communication
Control word (in register communication)
The control word (CW) is located in the output process image [
}
21] , and is transmitted from the controller
to the terminal.
Bit CW.15 CW.14 CW.13 CW.12 CW.11 CW.10 CW.9 CW.8 CW.7 CW.6 CW.5 CW.4 CW.3 CW.2 CW.1 CW.0
Name RegData: Reg R/W Reg. no.
Key
Bit Name Description
CW.15 ... CW.
8 RegData: One byte of data to be written to the register. The other byte is
transferred in the adjacent process data byte.
CW.7 Reg 1
bin
Register communication switched on
CW.6 R/W 0
bin
Read access
1
bin
Write access
CW.5 to CW.0 Reg. no. Register number:
Enter the number of the
register [ } 18] that you want to
- read with the input data word DataIN [ } 21] and the HighByte of the
status bytes (RegData) or
- write the output data word
DataOUT [
}
21] and the HighByte of
control word (RegData).
Status byte (for register communication)
The status word (SW) is located in the input process image [ } 21] , and is transmitted from terminal to the
controller.
Bit SW.15 SW.14 SW.13 SW.12 SW.11 SW.10 SW.9 SW.8 SW.7 SW.6 SW.5 SW.4 SW.3 SW.2 SW.1 SW.0
Name RegData: Reg R/W Reg. no.