A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
(ATN_FM)
(ETHNET)
(FP SCLK)
(POWER DOWN LOADER)
(RDY_FM)
E5_SDRAM_CS1
(FLASH)
(FP D_FM)
(Reset Audio and BTSC)
2.5V
3.3V
5V
1.8V
Caps with smaller capacitance values to be
closer to respective power pins compared to
those of larger values. All should be as
close as possible.
General decoupling cap placement:
(/RST_VI)
(INT_VI)
(VI_AVID)
(Input only)
(Input only)
(Ain_Sel2)
(Ain_Sel1)
(SCART)
(NC)
(SCART)
(FP D_HOST)
(/ETHER_IRQ)
A0
DMN8652 - BGA 388
BBKAV Corporation
Custom
2
12
Wednesday, June 01, 2005
Title
Size
Document Number
Rev
Date:
Sheet
of
E
5_S
DRA
M
_DQ
12
ATAPI2_DATA14
VI_D9
E
5_S
DRA
M
_DQ
5
HD2
HD12
ATAPI1_DATA3
ATAPI2_DATA13
ATAPI1_DATA14
MCONFIG
TRST_L
ATAPI1_DATA11
ATAPI2_DATA4
ATAPI2_DATA5
ATAPI2_ADD1
HD9
E5_GPIOx35
E5_/DTACK
TDI
E5_UART2_RX
VI_D5
E
5_S
DRA
M
_DQ
3
E5_AO_IEC958
ATAPI2_DATA12
ATAPI1_DATA1
HD1
VI_VSYNC
E
5_S
DRA
M
_DQ
24
HD3
ATAPI2_DATA9
E5_GPIOx29
VI_D2
HD4
HD11
TMS
ATAPI2_DATA1
ATAPI2_DATA10
ATAPI2_ADD2
HD15
ATAPI1_ADD3
ATAPI2_ADD3
E5_GPIO1
HD5
HD7
E5_AO_LRCK
E
5_S
DRA
M
_DQ
25
VI_D6
E
5_S
DRA
M
_DQ
7
ATAPI2_DATA2
ATAPI2_DATA7
TCK
E5_AO_SCLK
E
5_S
DRA
M
_DQ
31
E
5_S
DRA
M
_DQ
19
HD14
ATAPI1_DATA4
E
5_S
DRA
M
_DQ
0
E
5_S
DRA
M
_DQ
15
VI_D3
E
5_S
DRA
M
_DQ
10
TDO
E5_UART2_TX
HD6
HD0
E
5_S
DRA
M
_DQ
23
E
5_S
DRA
M
_DQ
14
VOE
ATAPI1_DATA13
ATAPI2_DATA0
E5_GPIO5
E5_GPIO0
ATAPI1_ADD0
ATAPI2_DATA6
ATAPI1_DATA5
E5_/DTACK
/E5_CS2
VI_D4
E
5_S
DRA
M
_DQ
8
VO_ACTIVE
E
5_S
DRA
M
_DQ
21
E
5_S
DRA
M
_DQ
2
HD10
E
5_S
DRA
M
_DQ
9
E
5_S
DRA
M
_DQ
6
VI_CLK0
E
5_S
DRA
M
_DQ
29
HD13
E
5_S
DRA
M
_DQ
22
ATAPI1_DATA7
ATAPI2_DATA11
ATAPI1_ADD1
ATAPI1_DATA10
E
5_S
DRA
M
_DQ
20
E5_GPIO2
/WAIT
E
5_S
DRA
M
_DQ
13
E5_AI_MCLKO
E
5_S
DRA
M
_DQ
16
ATAPI2_ADD4
E
5_S
DRA
M
_DQ
28
E5_AI_SCLK
MCONFIG
ATAPI1_DATA2
ATAPI2_ADD0
E
5_S
DRA
M
_DQ
26
E
5_S
DRA
M
_DQ
4
E
5_S
DRA
M
_DQ
30
E
5_S
DRA
M
_DQ
18
/E5_CS1
E5_GPIOx34
VO_HSYNC
ATAPI2_DATA8
E5_AI_FSYNC
ATAPI1_DATA8
E
5_S
DRA
M
_DQ
11
E
5_S
DRA
M
_DQ
27
ATAPI1_DATA0
HD8
ATAPI1_ADD2
ATAPI1_DATA15
E5_GPIO4
ATAPI2_DATA3
ATAPI1_DATA12
E
5_S
DRA
M
_DQ
1
ATAPI1_DATA9
E
5_S
DRA
M
_DQ
17
ATAPI2_DATA15
VI_D8
ATAPI1_DATA6
E5_AO_MCLKO
VI_D7
ATAPI1_ADD4
/E5_CS0
E5_GPIOx35
CLK_E5_CLKX
CLK_E5_CLKI
TRST_L
TCK
TDI
TMS
TDO
/E5_CS2
AO_2
AO_0
AO_3
AO_1
E5_GPIO7
E5_GPIO6
E5_GPIOx32
E5_GPIO3
E5_GPIOx31
E5_GPIOx34
E5_GPIOx29
E5_GPIOx45
E5_GPIOx36
E5_GPIO4
E5_GPIO5
E5_SIO_IRRX
E5_GPIO6
E5_GPIOx40
SPI_MOSI
CL
DI
SPI_MISO
CE
DO
SPI_SCK
SPI_CS2
SPI
_SC
K
SPI
_C
S2
SPI
_M
ISO
SPI
_M
O
SI
VO_VSYNC
AO_MCLKO 10
E
5_S
DRA
M
_DQ
S
1
3
/E5_CS0 6
E
5_S
DRA
M
_A
1
3
ATAPI2_ADD[4..0] 6
ATAPI2_DATA[15..0]
6
E
5_S
DRA
M
_DQ
S
0
3
E
5_S
DRA
M
_A
7
3
E
5_S
DRA
M
_A
3
3
U
SB_
D
0-
7
E5_MA4 5,6
Y/G_Out 11
E
5_S
DRA
M
_A
14
3
E5_MA2 5,6
/RST_ATAPI1 6
US
B
_O
C0
7
E
5_S
DRA
M
_CA
S
#
3
E
5_S
DRA
M
_A
5
3
VI_CLK0
9
Y_Out 11
AI_SCLK 10
VI_VSYNC
9
ATAPI1_DIOW_L 6
E5_GPIOx45 12
/E5_CS1 5
E
5_S
DRA
M
_W
E
#
3
B
IO
_LINK
_O
N
7
E5_GPIO1 9
ATAPI2_DMAACK_L 6
ATAPI1_INTRQ 6
E
5_S
DRA
M
_CLK
#0
3
E
5_S
DRA
M
_A
10
3
E
5_S
DRA
M
_A
11
3
/WAIT
5
BI
O
_PH
Y_
D
AT
A2
7
ATAPI1_DMARQ 6
E5_MA5 5,6
E
5_S
DRA
M
_A
8
3
VI_D[9..2]
9
AI_MCLKO 10
E5_GPIO3 10
Pr/R_Out 11
ATAPI2_DIOW_L 6
BI
O
_PH
Y_
D
AT
A5
7
SC
L
5,6,9,10
E5_GPIO2 5
BI
O
_PH
Y_
C
T
L1
7
E
5_S
DRA
M
_DQ
S
3
3
BI
O
_PH
Y_
D
AT
A0
7
AO_IEC958 5
/E5_WEL 5,6
E
5_IRT
X
1
6
E
5_S
DRA
M
_DQ
M
2
3
BI
O
_PH
Y_
C
T
L0
7
E
5_G
P
IO
x41
12
ATAPI2_INTRQ 6
E
5_S
DRA
M
_CLK
0
3
E5_SDRAM_DQ[31..0]
3
E
5_S
DRA
M
_A
0
3
VR
EF
3,4
E
5_S
DRA
M
_DQ
M
1
3
E
5_S
DRA
M
_DQ
M
0
3
E
5_S
DRA
M
_A
2
3
AI_D0 10
HD[15..0] 5,6
E
5_S
DRA
M
_CLK
E
3
E5_MA3 5,6
ATAPI2_DMARQ 6
E
5_S
DRA
M
_CS
0
3
E
5_S
DRA
M
_A
4
3
E
5_UA
R
T
2_RX
5
BI
O
_PH
Y_
D
AT
A4
7
U
SB_
D
0+
7
E
5_S
DRA
M
_A
6
3
/RST_ATAPI2 6
U
SB_
PO
0
7
E
5_S
DRA
M
_RA
S
#
3
CVBS_Out 11
E5_MA1 5,6
Pb/B_Out 11
ATAPI1_DATA[15..0]
6
AI_FSYNC 10
E
5_S
DRA
M
_CLK
#1
3
/SYS_RST 5,6
E
5_S
DRA
M
_A
9
3
BI
O
_L
R
EQ
7
E5_GPIO0 12
ATAPI1_DIOR_L 6
C_Out 11
BI
O
_PH
Y_
C
LK
7
BI
O
_PH
Y_
D
AT
A1
7
ATAPI1_IORDY 6
E
5_S
DRA
M
_CLK
1
3
E
5_S
DRA
M
_A
15
3
BI
O
_PH
Y_
D
AT
A6
7
B
IO
_LP
S
7
/E5_OE 5,6
ATAPI1_DMAACK_L 6
ATAPI2_DIOR_L 6
E
5_S
DRA
M
_DQ
M
3
3
SD
A
5,6,9,10
BI
O
_PH
Y_
D
AT
A3
7
E5_MA22 6
E
5_G
P
IO
x42
12
E5_ALE 5,6
E
5_S
DRA
M
_A
12
3
E
5_G
P
IO
x25
12
ATAPI2_IORDY 6
BI
O
_PH
Y_
D
AT
A7
7
E
5_S
DRA
M
_DQ
S
2
3
ATAPI1_ADD[4..0] 6
E5_GPIOx35
7
AO_D0
10
AO_D3
10
AO_D2
10
AO_D1
10
AO_SCLK
10
AO_FSYNC
10
E5_GPIO7 9
E5_GPIOx32
/E5_UDS 5
E5_/DTACK 5
E
5_G
P
IO
x36
7
E5_GPIO5 12
E5_GPIO4 12
E5_GPIOx33 9
IR_FMUTE 10,12
E
5_G
P
IO
x40
12
E
5_G
P
IO
x24
12
CE
9
CL
9
DO
9
DI
9
E
5_UA
R
T
2_T
X
5
RDS_DATA 9
E5_GPIOx31 9
E5_GPIOx34 12
U
SB_
D
1+
7
U
SB_
D
1-
7
US
B
_O
C1
7
U
SB_
PO
1
7
GND
GND
GND
V33
GND
V33_E5_DAC_AVDD
GND
GND
V33
E5_VDDREF
GND
V18_E5_DAC_DVDD
V33_E5_USB
GND
V33
E5_AVDD
E
5_V
5B
IA
S
GND
S
S
T
L2_V
DD
E5_VCORE
E5_VPAD
GND
GND
GND
V33
VCC
E5_V5BIAS
V25
V33
V18
SSTL2_VDD
E5_VPAD
V18_E5_DAC_DVDD
V33_E5_DAC_AVDD
V33_E5_USB
E5_VDDREF
E5_AVDD
E5_VDDX
GND
GND
E5_VCORE
E5_VCORE
E5_AVDD
E5_VPAD
E5_VDDREF
E5_VDDX
GND
GND
GND
GND
GND
GND
SSTL2_VDD
VO_GND
GND
VO_GND
V33
V33
GND
E5_VDDX
GND
VCC
C10
103
TP3
1
Y1
13.5MHZ
RX1
1
C1
27PF
C9
104
TX1
1
C2
27PF
R262
*22
D1
*LL60P
1
2
R38
22
R258
*10K
TP1
1
R89
10K
ADDR
DATA
SIO
SDRAM I/F
RST-
MASTER
SLAVE
MCONFIG
CS-
RD-
DMAREQ
A0
A1
A2
HINT-
RD
WAIT-
DTACK-
D31
D30
D29
D28
D27
D26
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D4
D3
D2
D1
D0
UDS-
LDS-
PCMCIA_IOW-
PCMCIA_IOR-
WR-
D25
D24
D23
D22
D21
D20
D19
D18
MA[21]
MA[20]
MA[19]
MA[18]
MA[17]
MA[16]
MA[15]
MA[14]
MA[13]
MA[12]
MA[11]
MA[10]
MA[9]
MA[8]
MA[7]
MA[6]
CONTROL
ATAPI2 I
/
F
ATAPI I
/
F
SD/CD
SBP
SBP_D[7]
SBP_D[6]
SBP_D[5]
SBP_D[4]
SBP_D[3]
SBP_D[2]
SBP_D[1]
SBP_D[0]
SD_ERROR
SD_SECSTART
SBP_CLK
SBP_REQ
SBP_RD
SBP_ACK
SBP_FRAME
SD_D[0]
SD_D[1]
SD_D[2]
SD_D[3]
SD_D[4]
SD_D[5]
SD_D[6]
SD_D[7]
SD_CLK
SD_ACK
SD_RDREQ
SD_WRREQ
DATA
ADDR
CONTROL
IDC
UART1
UART2
SPI
IR
CS10-
CS11-
GPIOx[25] GPIOx[24]
GPIOx[42]
GPIOx[41]
CS7-
GPIOx[39]
GPIOx[40]
GPIOx[38] GPIOx[37]
HOST I
/
F
VDENC
0
1
2
CPST Y
-
C CPST
-
G/Y
Y
-
B/Pb C CPST
R/Pr C CPST
SEL
PEC
GPIOx[45]
GPIOx[29]
2nd
24-bit
VI_D0
VI_D1
VI_D2
VI_D3
VI_D4
VI_D5
VI_D6
VI_D7
VI_D8
VI_D9
VO_D16
VO_D17
VO_D18
VO_D19
VO_D20
VO_D21
VO_D22
VO_D23
VIO
GPIOx[30]
GPIOx[0]
GPIOx[1]
GPIOx[2]
GPIOx[3]
GPIOx[4]
GPIOx[5]
GPIOx[6]
GPIOx[7]
GPIOx[8]
GPIOx[9]
GPIOx[10]
GPIOx[11]
GPIOx[12]
GPIOx[13]
GPIOx[14]
GPIOx[15]
VOUT
VIN
JTAG
SYSTEM
GPIOx[31]
GPIOx[34]
GPIO[7]
GPIO[6]
AIN
AOUT
GPIOx[35]
CS[9]-
CS[8]-
USB
1394
POWER
GND
PADS
CORE
SDRAM
SDR
DDR
3.3V
2.5V
5V
BIAS
3.3V
1.8V
3.3V
PLL PLL
VREF
GPIOx[43] GPIOx[44]
DACO
GPIOx[36]
CS6-
GPIOx[23]
GPIOx[22]
GPIOx[21]
GPIOx[20]
GPIOx[19]
GPIOx[18]
GPIOx[17]
GPIOx[16]
CD_DATA
CD_LRCK
CD_BCK
CD_C2PO
vout
vin
Y CPST
-
TOP VIEW
3.3V ONLY
2nd
VO_D0
VO_D7
VO_D6
VO_D5
VO_D4
VO_D3
VO_D2
VO_D1
vout
VI_D10
VI_D11
VI_D12
VI_D13
VI_D14
VI_D15
20-bit
vin
POWER
3.3V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
3.3v only
GND
DIGITAL
GPIOx[33]
GPIOx[32]
VI_D16
VI_D17
VI_D18
VI_D19
All the singals with * and
the ATAPI-2 I/F are not
available in 308-pin
package
NOTE:
E5.1-BGA-388-A
J3
AE1
9
L4
M4
M3
J2
J1
K3
K2
J4
L3
L2 L1 H3 K1
AC
12
AC
7
D21
C21
T1
6
R16
AC
13
AC
14
AC
15
D14 D15 D19 D20 P4 R4 T4
AA4 AA2
3
AC
6
AC
21
D11 D12 D13
C22 D23 M2
3
N24 P2
4
R24 T2
4
U23
C23 L11 L12 L13 L14 L15 L16 M1
1
M1
2
M1
3
M1
4
M1
5
M1
6
N11 N12 N13 N14 N15 N16 P1
1
P1
2
P1
3
P1
4
P1
5
P1
6
R11 R12 R13 R14 R15 T1
1
T1
2
T1
3
T1
4
T1
5
AF5
AE5
AF19
AF18
AF17
AF16
AE6
AC8
AF6
AD7
AE7
AF7
AD9
AC9
AE8
AF8
AD11
AE12
AF11
AC11
AF12
AE13
AE11
AD14
AE15
AD13
AD16
AC16
AE17
AD15
AE16
AD17
D10
Y1
V1
V4
R1
W2
W3
T3
Y2
W1
V3
U4
P1
W4
V2
U2
T2
R3
P2
N1
M1
M2
N2
N3
P3
R2
T1
U1
U3
AF15
AF13
AE18
AC17
AE14
AE10
AE9
AD8
AF9
AF14
AF10
AD10
AD
21
AC
19
AF
22
AE2
3
AC
22
AE2
4
AC
20
AF
24
AE2
0
AF
23
AE2
2
AD
22
AF
21
AE2
1
AC
18
AD
18
AD
20
AD
19
AF
20
D3 D2 D5 D4 B1
B3 C3 C5 C4 B2
D1
C1
C2
Y2
5
W2
4
V2
3
Y2
6
V2
4
W2
6
V2
5
V2
6
N25
U26
R26
P2
6
T2
5
P2
5
T2
6
U25
M2
5
M2
4
L26
L25
L23
K2
6
K2
5
K2
4
H23
G2
6
H24 H25
J2
4
J2
5
J2
3
J2
6
W2
5
U24
R25
L24
H26
N26
M2
6
K2
3
AC
25
AB2
3
AA2
4
AC
26
AB2
4
AD
25
AD
26
AE2
5
AC
23
AF
25
AD
24
AE2
6
AC
24
AF
26
AD
23
AB2
5
AA2
5
Y2
4
W2
3
AA2
6
N23
P2
3
R23
T2
3
D22
G24
G23
F26
G25
F24
E25
F25
E23
D25
A23
B25
E26
D26
E24
D24
C26
B24
A1
A2
H1
H4
C9
D9
B8
A9
B7
D8
C7
C19
B19
B23
B22
A22
B21
C25
B26
C24
A26
B16
C16
D16
B17
C17
D17
B18
C18
A19
D18
B20
A21
A17
A20
C20
A18
A10
B10
B11
A11
C11
C12
B12
A12
B13
A13
C13
C14
B14
A14
A15
C15
B15
C10
B9
C8
A16
AB2
6
Y2
3
AD6
AF3
AC5
AE4
AF4
AD5
AD4
AE2
AD3
AC4
AF2
AE3
AF1
AE1
AD2
AC3
AB4
AD1
AC2
AB3
AC1
AB2
AA3
AB1
AA2
Y4
AA1
Y3
E2 E1 G1 G2 F2 F1 G3 G4
A3
B4
A4
B5
A5
A6
C6
A7
D6
AD12
AC10
A24
A25
H2
D7
B6
A8
E4 F4 E3 F3
F2
3
K4 N4
BI
O
_PH
Y_
D
AT
A0
IRRX
BI
O
_PH
Y_
D
AT
A1
BI
O
_PH
Y_
D
AT
A2
BI
O
_PH
Y_
D
AT
A3
BI
O
_PH
Y_
D
AT
A4
BI
O
_PH
Y_
D
AT
A5
BI
O
_PH
Y_
D
AT
A6
BI
O
_PH
Y_
D
AT
A7
BI
O
_PH
Y_
C
T
L0
BI
O
_PH
Y_
C
T
L1
B
IO
_LRE
Q
B
IO
_LP
S
B
IO
_LINK
_O
N
BI
O
_PH
Y_
C
LK
V
DD_P
A
D
1
5V
_B
IA
S
0
5V
_B
IA
S
1
VSS_
PC
2_
C
T
R
1
VSS_
PC
2_
C
T
R
37
VSS_
PC
2_
C
T
R
38
V
DD_P
A
D
2
V
DD_P
A
D
3
V
DD_P
A
D
4
V
DD_P
A
D
5
V
DD_P
A
D
6
V
DD_P
A
D
7
V
DD_P
A
D
8
V
DD_P
A
D
9
V
DD_P
A
D
10
V
DD_P
A
D
11
V
DD_CO
RE
1
V
DD_CO
RE
2
V
DD_CO
RE
3
V
DD_CO
RE
4
V
DD_CO
RE
5
V
DD_CO
RE
6
V
DD_CO
RE
7
V
DD_25V
1
V
DD_25V
2
V
DD_25V
3
V
DD_25V
4
V
DD_25V
5
V
DD_25V
6
V
DD_25V
7
V
DD_25V
8
VSS_
PC
2_
C
T
R
2
VSS_
PC
2_
C
T
R
3
VSS_
PC
2_
C
T
R
4
VSS_
PC
2_
C
T
R
5
VSS_
PC
2_
C
T
R
6
VSS_
PC
2_
C
T
R
7
VSS_
PC
2_
C
T
R
8
VSS_
PC
2_
C
T
R
9
VSS_
PC
2_
C
T
R
10
VSS_
PC
2_
C
T
R
11
VSS_
PC
2_
C
T
R
12
VSS_
PC
2_
C
T
R
13
VSS_
PC
2_
C
T
R
14
VSS_
PC
2_
C
T
R
15
VSS_
PC
2_
C
T
R
16
VSS_
PC
2_
C
T
R
17
VSS_
PC
2_
C
T
R
18
VSS_
PC
2_
C
T
R
19
VSS_
PC
2_
C
T
R
20
VSS_
PC
2_
C
T
R
21
VSS_
PC
2_
C
T
R
22
VSS_
PC
2_
C
T
R
23
VSS_
PC
2_
C
T
R
24
VSS_
PC
2_
C
T
R
25
VSS_
PC
2_
C
T
R
26
VSS_
PC
2_
C
T
R
27
VSS_
PC
2_
C
T
R
28
VSS_
PC
2_
C
T
R
29
VSS_
PC
2_
C
T
R
30
VSS_
PC
2_
C
T
R
31
VSS_
PC
2_
C
T
R
32
VSS_
PC
2_
C
T
R
33
VSS_
PC
2_
C
T
R
34
VSS_
PC
2_
C
T
R
35
VSS_
PC
2_
C
T
R
36
CS5-
CS4-
CS3-
CS2-
CS1-
CS0-
MA[26]
MS[25]
MA[24]
MA[23]
MA[22]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCONFIG
ATAPI_RESET_L
ATAPI_DMAACK_L
ATAPI_DMARQ
ATAPI_IORDY
ATAPI_INTRQ
ATAPI_DIOR_L
ATAPI_DIOW_L
AtapiAddr0
AtapiAddr1
AtapiAddr2
AtapiAddr3
AtapiAddr4
ATAPI_DATA15
ATAPI_DATA14
ATAPI_DATA13
ATAPI_DATA12
ATAPI_DATA11
ATAPI_DATA10
ATAPI_DATA9
ATAPI_DATA8
ATAPI_DATA7
ATAPI_DATA6
ATAPI_DATA5
ATAPI_DATA4
ATAPI_DATA3
ATAPI_DATA2
ATAPI_DATA1
ATAPI_DATA0
ALE
OE-
RST-
UWE-
GPIO1
GPIO2
GPIO3
GPIO0
GPIO4
LWE-
GPIO5
DTACK-
IDC_CLK
IDC_DA
T
UA
RT
2_RX
UA
RT
2_T
X
*U
A
R
T
2_CT
S
*U
A
R
T
2_RT
S
UA
RT
1_RX
UA
RT
1_T
X
UA
RT
1_CT
S
UA
RT
1_RT
S
SPI
_M
O
SI
SPI
_M
ISO
SPI
_C
S0
SPI
_C
S1
SPI
_C
S2
S
P
I_CLK
*SPI
_C
S3
IRTX
1
*I
R
T
X2
A
V
DD0
A
V
DD1
A
V
DD2
A
V
DD3
V
DDX
A
G
ND0
A
G
ND1
A
G
ND2
A
G
ND3
G
NDX
V
DD_RE
F
R_RE
F
VSS_
R
EF
S
DRA
M
_DQ
2
S
DRA
M
_DQ
1
S
DRA
M
_DQ
0
S
DRA
M
_DQ
3
S
DRA
M
_DQ
4
S
DRA
M
_DQ
5
S
DRA
M
_DQ
6
S
DRA
M
_DQ
7
S
DRA
M
_DQ
15
S
DRA
M
_DQ
9
S
DRA
M
_DQ
12
S
DRA
M
_DQ
14
S
DRA
M
_DQ
10
S
DRA
M
_DQ
13
S
DRA
M
_DQ
11
S
DRA
M
_DQ
8
S
DRA
M
_DQ
16
S
DRA
M
_DQ
17
S
DRA
M
_DQ
18
S
DRA
M
_DQ
19
S
DRA
M
_DQ
20
S
DRA
M
_DQ
21
S
DRA
M
_DQ
22
S
DRA
M
_DQ
23
S
DRA
M
_DQ
24
S
DRA
M
_DQ
25
S
DRA
M
_DQ
27
S
DRA
M
_DQ
26
S
DRA
M
_DQ
28
S
DRA
M
_DQ
29
S
DRA
M
_DQ
30
S
DRA
M
_DQ
31
S
DRA
M
_DQ
S
0
S
DRA
M
_DQ
M
0
S
DRA
M
_DQ
S
1
S
DRA
M
_DQ
S
2
S
DRA
M
_DQ
S
3
S
DRA
M
_DQ
M
1
S
DRA
M
_DQ
M
2
S
DRA
M
_DQ
M
3
S
DRA
M
__A
0
S
DRA
M
__A
1
S
DRA
M
__A
2
S
DRA
M
__A
3
S
DRA
M
__A
4
S
DRA
M
__A
5
S
DRA
M
__A
6
S
DRA
M
__A
7
S
DRA
M
__A
8
S
DRA
M
__A
9
S
DRA
M
__A
10
S
DRA
M
__A
11
S
DRA
M
__A
12
*S
DRA
M
__A
13
S
DRA
M
__A
14
S
DRA
M
__A
15
S
DRA
M
_CA
S
_L
S
DRA
M
_RA
S
_L
S
DRA
M
_CK
E
S
DRA
M
_W
E
_L
S
DRA
M
_CLK
0
S
DRA
M
_CLK
_L0
S
DRA
M
_CLK
1
S
DRA
M
_CLK
_L1
SD
R
A
M_
VR
EF
AO_D0
AO_D1
AO_D2
AO_D3
AO_SCLK
AO_FSYNC
AO2_D0*
A2_SCLK*
A2_FSYNC*
AO_IEC958
AO_MCLKI
AI2_D*
AI_D0
AI_D1
AI_SCLK
AI_FSYNC
AI_MCLKI
CLKI
CLKX
CLKO
BYPASS_PLL
RSTO*
EPD_L*
TCK
TDI
TDO
TMS
TRST_L
VI_D0
VI_D1
VI_D2
VI_D3
VI_D4
VI_D5
VI_D6
VI_D7
VI_D8
VI_D9
VIO_D0*
VIO_D1*
VIO_D2*
VIO_D3*
VIO_D4*
VIO_D5*
VIO_D6*
VIO_D7*
VIO_D8*
VIO_D9*
VI_E0
VI_VSYNC0
VI_CLK0
VI_E1
VI_VSYNC1*
VI_CLK1*
VO_D0
VO_D1
VO_D2
VO_D3
VO_D4
VO_D5
VO_D6
VO_D7
VO_D8*
VO_D9*
VO_D10*
VO_D11*
VO_D12*
VO_D13*
VO_D14*
VO_D15*
VO_E*
VO_ACTIVE*
VO_HSYNC*
VO_VSYNC*
VO_CLK
S
DRA
M
__A
17
S
DRA
M
__A
16
ATAPI2_RESET_L
ATAPI2_DMAACK_L
ATAPI2_DMARQ
ATAPI2_IORDY
ATAPI2_INTRQ
ATAPI2_DIOR_L
ATAPI2_DIOW_L
Atapi2Addr0
Atapi2Addr1
Atapi2Addr2
Atapi2Addr3
Atapi2Addr4
ATAPI2_DATA15
ATAPI2_DATA14
ATAPI2_DATA13
ATAPI2_DATA12
ATAPI2_DATA11
ATAPI2_DATA10
ATAPI2_DATA9
ATAPI2_DATA8
ATAPI2_DATA7
ATAPI2_DATA6
ATAPI2_DATA5
ATAPI2_DATA4
ATAPI2_DATA3
ATAPI2_DATA2
ATAPI2_DATA1
ATAPI2_DATA0
Dpl
us
_0
Dm
inus
_0
Hos
t_P
O
_0
Hos
t_O
C_0
Dpl
us
_1*
Dm
inus
_1*
Hos
t_P
O
_1*
Hos
t_O
C_1*
DAC1
DAC0bar
DAC2
DAC1bar
DAC3
DAC4
DAC_Vdd0(3.3v)
DAC5
DAC_Vdd1(3.3v)
CS0_8BIT
WAIT-
AI_MCLKO
AO_MCLKO
US
B
_48M
HZ
*
DAC_Dvdd (1.8v)
DAC_Dvss
DAC6
US
B
_A
vdd0(
3.3v
)
US
B
_A
vdd1(
3.3v
)
U
SB_
VSS0
U
SB_
VSS1
V
DD_CO
RE
8
V
DD_CO
RE
9
V
DD_CO
RE
10
R21
*10K
R22
*10K
TP6
1
R42
10K
R44
10K
R46
10K
R261
*22
R41
10K
R23
*0
R20
10K
R39
4.7K
R259
*10K
+
CA2
100u/16
C8
104
+
C24
10u/16 SMT
R257
*10K
C52
104
R256
*10K
R34
22
C36
103
TP5
1
R33
*22
C37
103
C55
104
R260
*22
C14
102
R35
22
C15
102
C12
104
C16
102
R37
22
C54
103
C53
103
R36
22
C17
104
C51
103
C56
102
R32
22
C7
103
+
C25
10u/16 SMT
+
C26
10u/16 SMT
R12
10K
C40
104
R9
10K
C42
104
R4
10K
C13
104
C41
104
R6
10K
C43
104
R2
10K
C27
104
R1
10K
C45
104
C28
104
C44
104
C29
104
C31
104
L3
B221
C32
104
+
C11
10u/16 SMT
L4
B221
C30
104
R43
10K
+
C4
10u/16
+
C38
10u/16
C5
104
+
C39
10u/16 SMT
CN1
*5P1.0
1
2
3
4
5
R31
22
L1
B221
C49
103
C3
104
C50
104
R19
*10K
+
CA1
47u/16
C19
104
L2
B221
C18
104
FB1
B221
+
C23
10u/16 SMT
R30
DNS_0
C35
102
R13
10K
C20
104
SKT-U1
SKT-BGA388
R10
10K
C21
104
R15
10K
C22
104
R17
10K
C34
102
R7
10K
C33
102
R5
10K
C47
102
R8
*10K
C6
104
C48
102
R25
22
R11
10K
C46
102
R27
22
R16
10K
R26
22
R14
*10K
R24
*22
R18
*10K
R45
1.2K
1%
R29
22
D2
IN4148
1
2
R3
*10K
D3
IN4148
1
2
TP2
1
R263
*22
R28
22
25
Содержание DW9951S
Страница 1: ...SERVICE MANUAL DW9951S R Ver 0 0 ...
Страница 3: ...1 ...
Страница 4: ...2 ...
Страница 5: ...3 ...
Страница 6: ...BLOCK DIAGRAM 4 ...
Страница 7: ...5 EXPLODED VIEW ...
Страница 15: ...14 13 ...
Страница 16: ...15 14 ...
Страница 17: ...16 15 ...
Страница 18: ...17 IS2 16 ...
Страница 24: ...22 ...
Страница 26: ...11 Terminal for External Connection Outline Drawing 24 ...
Страница 38: ...36 ...
Страница 39: ...37 ...
Страница 40: ...38 ...
Страница 41: ...39 ...
Страница 50: ...48 ...
Страница 51: ...49 ...
Страница 52: ...50 ...
Страница 53: ...51 ...
Страница 55: ...53 ...
Страница 56: ...54 ...
Страница 57: ...55 ...
Страница 58: ...56 ...
Страница 60: ...58 ...
Страница 61: ...59 ...
Страница 73: ...BBK ELECTRONICS CORP LTD 23 Bubugao Road Wusha Chang an Dongguan China http www gdbbk com ...
