BBK DK1001S, Руководство по обслуживанию

Страница: 18 / 47

SDRAM 16Mb H-die(x16) CMOS SDRAM
Rev. 1.4 May 2004
The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated
with SAMSUNG
′
s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/
O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten-
cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
• 3.3V power supply
• LVTTL compatible with multiplexed address
• two banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
•
Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 32ms refresh period (2K cycle)
GENERAL DESCRIPTION
FEATURES
512K x 16Bit x 2 Banks SDRAM
ORDERING INFORMATION
Part NO. MAX Freq. Interface Package
K4S161622H-TC55 183MHz
LVTTL
50pin
TSOP(II)
K4S161622H-TC60 166MHz
K4S161622H-TC70 143MHz
K4S161622H-TC80 125MHz
Row & Column address configuration
Organization Row Address Column Address
1Mx16 A0~A10 A0-A7