MT1379
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE
MTK CONFIDENTIAL, NO DISCLOSURE
controller changes the mode and speed of operation according to servo register setting. The PWM generator generates
pulse -width -modulated signal to drive disc spindle motor driver.
CSS/CPPM
The CSS/CPPM module provides functions necessary for decoding discs conforming to CSS/CPPM specification.
System Parser
The system parser is used to help the system controller to decode DVD/SVCD/VCD bitstream just after the channel decoder
performing error correction. Acting as a DMA master, it moves bitstream data from RSPC buffer to video, audio, or sub-picture
buffer according to system controller request. It also decrypts the scramble data of the CSS/CPPM sectors. Another function of
system parser is providing system controller/DSP a DRAM memory copy controller to enhance system controller/DSP performance.
Video Decoder
The primary function of MT1379 is to support MPEG1 and MPEG2 video decoding. The video decode engine comprises of
variable length decoder (VLD), inverse transformer (IT), motion compensator (MC), and block reconst ructor (BR). The video
decode engine decodes the variable length encoded symbols in MPEG bitstream and performs inverse scan, inverse
quantization, mismatch control and inverse discrete cosine transform onto the variable length decoded data. The motion
compensator fetches prediction data from reference picture buffer according to motion vectors and motion prediciton mode for P
and B pictures. Finally, the block reconstructor combines both the results of inverse transformer and motion compensator to derive
the reconstructed image macroblock and write back to picture buffer.
The video decode engine can also support JPEG and BMP file decoding by common image compression hardware kernels.
Video Output
The Video Output unit contains Video Processor, SPU, OSD, Cursor, TV encoder units, it performs
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Reading decoded video from DRAM buffer
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Scaling the image
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Gamma/Brightness/Hue/Saturation adjustment and edge enhancement
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Reading and decoding SPU and OSD data from DRAM buffer
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Generating hardware cursor image
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Merging the video data, SPU, OSD and cursor
Video Processor
The Video Processor unit controls the transfer of video data stored in the DRAM to an internal or external TV encoder. It uses
FIFOs to buffer outgoing luminance and chrominance data, and performs YUV420 to YUV422 conversion and arbitrary
vertical/horizontal decimation/interpolation, from 1/4x to 256x. With this arbitrary ratio scaling capability, the Video Processor
can perform arbitrary image conversion, such as PAL to NTSC, NTSC to PAL, MPEG1 to MPEG2, Letterbox, Pan-Scan
conversion or zoom in, zoom out. It is also capible of interlace to progressive conversion.
The Video Processor unit performs the following functions:
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Requests and receives the decoded picture data from the picture buffer in external DRAM for display
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Resample vertical data to create 4:2:2 sample format
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Optionally performs vertical/horizontal resampling of both luminance and chrominance data
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Performs optional Gamma correction, luminance/chrominance adjustment, and edge enhancement
The V ideo Processor unit contains two 2-tap vertical filters for luminance and chrominance . These filters are used to
interpolate and reposition luminance and chrominance line to improve picture quality. These filters are capble of generating
up to eight, unique subline value between two consecutive scan lines. The generation of lines depends on the ratio between
the height of the source image and the target image. In applications where DRAM bandwidth are critical the filters can be
configured as simple line-repeating to reduce the DRAM bandwidth required.
The Video Processor unit integrates two separate horizontal postprocessing filter, a simple 2-tap linear horizontal filter and
an 8-tap programmable filter. These filters are provided for scaling images horizontally along the scan line. These two filters
is capable of generating up to eight, unique subpixel values between two consecutive pixels on a scan line. The generation
of pixels depends on the ratio between the width of the source image and the target image.
SPU
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Содержание BBK916S
Страница 1: ...SERVICE MANUAL BBK916S...
Страница 4: ...2 3...
Страница 13: ...7 MPEG BOARD CHECK WAVEFORM 7 1 27MHz WAVEFORM DIAGRAM 7 2 IC5L0380R PIN 2 WAVEFORM DIAGRAM 11...
Страница 44: ...42 FRONT SCHEMATIC DIAGRAM...
Страница 46: ...POWER BOARD SCHEMATIC DIAGRAM 44...
Страница 48: ...46 OK SCHEMATIC DIAGRAM...
Страница 50: ...48 OUTPUT BOARD SCHEMATIC DIAGRAM...
Страница 55: ...53 MIAN SCHEMATIC DIAGRAM...
Страница 56: ...54 MIAN SCHEMATIC DIAGRAM...