Basler A400K, Руководство пользователя

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Camera Interface
Basler A400k 2-13
DRAFT
2.5 Output Signals
Data is output from the A400k using the Camera Link standard. The Pixel Clock signal is
described in Section 2.5.1, the Line Valid signal in Section 2.5.2, the Frame Valid signal in Section
2.5.3, and the video data in Section 2.5.4. Video Data output is described in Sections
2.5.5 and
2.5.6 . Section 2.5.8 describes the flash trigger signal. SerTFG (“Serial to Frame Grabber“) of the
serial communication is described in Section 2.6 .
2.5.1 Pixel Clock
On the A402k, the pixel clock is assigned to the strobe port (TxClk pin) on Camera Link transmitter
X as defined in the Camera Link standard and as shown in Table
2-5 . On the A403k , the pixel
clock is assigned to the strobe port on Camera Link transmitter X and Camera Link transmitter Y
as defined in the standard and as shown in Tables
2-6 and 2-7 . On the A404k, the pixel clock is
assigned to the strobe port on transmitters X, Y and Z as defined in the standard and as shown in
Tables
2-8, 2-9 and 2-10 . The pixel clock is used to time the sampling and transmission of pixel
data. The Camera Link transmitter(s) used in A400k cameras require pixel data to be sampled and
transmitted on the rising edge of the clock.
The frequency of the pixel clock is 50 MHz. For the A402k
,
on each Pixel Clock signal, two pixels
are transmitted at 8 bit or 10 bit depth. For the A403k, on each Pixel Clock signal, four pixels are
transmitted at 8 bit or 10 bit depth. For the A404k, on each Pixel Clock signal, four pixels are
transmitted at 8 bit or 10 bit depth when the camera is set for 4 tap output. When an A404k is set
for 8 tap output, eight pixels at a depth of 8 bits are transmitted on each Pixel Clock signal.
2.5.2 Line Valid Bit
As shown in Figures 2-9 through 2-13 , the line valid bit indicates that a valid line is being
transmitted. Pixel data is only valid when this bit is high. On the A402k, 1176 pixel clocks are
required to transmit one full line. On the A403k, 588 pixel clocks are required to transmit one full
line. On the A404k, 588 pixel clocks are required to transmit one full line when the camera is set
for 4 tap output and 294 pixel clocks are required when the camera is set for 8 tap output.
On the A402k, line valid is assigned to the line valid port on Camera Link transmitter X as defined
in the Camera Link standard. On the A403k, line valid is assigned to the line valid ports on Camera
link transmitters X and Y as defined in the standard. On the A404k, line valid is assigned to the
line valid ports on transmitters X, Y and Z as defined in the standard (see Tables
2-5 through 2-10 ).
2.5.3 Frame Valid Bit
As shown in Figures 2-9 through 2-13 , the frame valid bit indicates that a valid frame is being
transmitted. Pixel data is only valid when the frame valid bit and the line valid bit are both high.
One frame can contain 2 to 1726 Line Valid signals.
On the A402k, frame valid is assigned to the frame valid port on Camera Link transmitter X as
defined in the Camera Link standard. On the A403k, frame valid is assigned to the frame valid
ports on Camera link transmitters X and Y as defined in the standard. On the A404k, frame valid
is assigned to the frame valid ports on transmitters X, Y and Z as defined in the standard. (See
Tables
2-5 through 2-10 ).