7.1 Block diagram
Block diagram 7.1
7.1
Block diagram
W1
MR
TW
ICE power
2ch Amp
ICE power
2ch Amp
W2
SMPS
Mains
Signal Processing
DSP
ADSP21478
Codec
AD1939
Ch3_out
TDM
Ch0_out
Ch1_out
Ch2_out
Ch4_out
Ch5_out
Ch6_out
Ch7_out
PA
int
erf
.#
1
PA
in
terf.
#2
Ch4+
Ch4-
PA
int
er
f.
#3
Ch0_in
Ch1_in
Ch0-1_in
Ch2-3_in
Ch0-1_in
Ch2-3_in
Training
Input_Sel
(A0-5)
Amp_En
Amp_En
Amp_En
Amp_En
BTL_sync2
BTL_sync1
BTL_sync3
GND
GND
GND
Sense_GND
Sense_GND
ADC
SPI_A
Flash
POR
WDT
PQR_RST_N
NT
C
Line
Sense
ATI
Line_Sense
PL_DATA
ATI
TX
LE
Ds
DC/DC
+/-12V
5V_SB
3V3
3V3_A
1V2
+/-12V
5V_SB
3V3
3V3_A
1V2
Pwr.
Logic
Pwr_En
PL_ON
Switch
signals
SW0 - SW9
SPI_A
Bus
SMPS_En
Pwr_Hold
Buffers
Ch0-1
Buffers
Ch2
Gain
Ranging
+/- 12V
+/-30V
-18V
PL
RJ45
PL_L
LED
driver
Red/Green (PWM)
De
bu
g
&
JTAG
ICE power
2ch Amp
PL
RJ45
SW2
(Line_EN_-dB)
OC
ATI
RJ45
PL_R
Signal switch
Par -> ser
2 x 8
SPI_A
Red/Green (PWM)
JTAG in RJ45/
ATI connector
Monitor_Bus
Monitor3
Monitor4
Monitor6
Monitor5
Vclip
PL_ON
RX
ATI_ON
ATI_ON
SPI_B
PL/Line/Line2
L/R/Mono
F/W/C
Signal
Switch
Monitor2
Monitor1
Monitor6
Monitor4
Monitor2
Monitor5
Monitor3
Monitor1
Sum
Buffer
Sum
Buffer
Sum
Buffer
Sum
Buffer
Gain
Ranging
Ch2_in
Ch3_in
Ch3+
Ch3-
NTC1
NTC2
NTC3
NTC4
Vclip
WDT_Pulse
ADC_NTC_MUX_SEL
(A0-2)
Line_Sense
12.288MHz
CLK
Codec_RST
SW1
(Line_EN)
Ch2+
Ch2-
Ch0+
Ch0-
Ch1+
Ch1-
Sense_GND
Ch5+
Ch5-
ATI
SPDIF
Switch
signals
SW8 - SW11
PQR_RST_N
JTAG
Thermal
Power
5V SB
Amp_Therm
Amp_OC
3.3 V
3.3 V
1.2 V
HW ver.
OC
Vclip
Thermal
OC
Vclip
Thermal
OC
Vclip
Thermal
V.CON
+/-30V
-18V
+/-30V
-18V
+/-5V
+/-5V
+/-5V
NTC
Vdrive control
not present in all versions
Содержание BeoLab 12-3
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