The 845D-AV MAINBOARD
Ver 3.x
Page 29
Managing The PC BIOS
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DRAM Timing Selectable
This field determines the DRAM read/write timing. The performance parame-
ters of the memory chips (DRAM) you have installed will determine the value
in this field. Do not change the value from the factory setting unless you install
new memory that has a different performance rating than the original DRAMs.
CAS Latency Time
The time delay (in clock cycles, CLKS) that passes before the SDRAM starts to
carry out a read command after it has been received. The number of CLKs that
occur before the first part of a burst transfer is completed is also determined
by this field.
DRAM RAS# to CAS# Delay
When the DRAM is refreshed, both rows and columns are addressed sepa-
rately. This setup allows you to determine the timing of the transition from
Row Address Strobe (RAS) to Column Address Strobe (CAS).
DRAM RAS# Precharge Time
If the DRAM is not continually refreshed it’s data will be lost. DRAM is normally
refreshed as a result of a single request. This field lets you select the number
of CLKs allocate for the RAS to accumulate its charge before the DRAM is re-
freshed. If there is not sufficient time then the refresh may be incomplete and
some of the data can be lost.
DRAM Data Integrity Mode
Error Checking and Correction (ECC) should only be used in conjunction with a
special 72-bit ECC RAM. If you are using ECC RAM you should select ECC.
This feature will enable the system to detect and correct single-bit errors and
detect (not correct) double-bit errors. If you do not have ECC RAM then select
Non-ECC (the default mode).
