AXIOMTEK SHB250R, Руководство пользователя

Страница: 76 / 96

SHB250R Intel LGA1151 Processor PICMG1.3 Half-size CPU Board
70 Digital I/O
Register 1: Output port register.
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit
values in this register have no effect on pins defined as inputs. Reads from this register return
the value that is in the flip-flop controlling the output selection, not the actual pin value.
Bit Symbol Access Value Description
7 O7 R 1*
Reflects outgoing logic levels of pins defined as
outputs by Register 3.
6 O6 R 1*
5 O5 R 1*
4 O4 R 1*
3 O3 R 1*
2 O2 R 1*
1 O1 R 1*
0 O0 R 1*
* : Default value
Register 3: Configuration register.
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to V
DD
.
Bit Symbol Access Value Description
7 C7 R/W 1*
Configure the directions of the I/O pins.
0 = Corresponding port pin enabled as an output.
1 = Corresponding port pin configured as input
(default value).
6 C6 R/W 1*
5 C5 R/W 1*
4 C4 R/W 1*
3 C3 R/W 1*
2 C2 R/W 1*
1 C1 R/W 1*
0 C0 R/W 1*
* : Default value