AXIOMTEK MANO500 Series, Руководство пользователя

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MANO500 Mini ITX Motherboard
Board and Pin Assignments 15
2.4.7 LVDS Signal Header (CN9)
This motherboard has a 20x2-pin p=1.00mm header for LVDS panel interface.
Note

CN9 is co-layout with eDP connector (CN19); they can
’t be accessed
simultaneously.

LVDS header P/N (CN9): GEAN-LEA electronic GLA1001WV-S-2x20.
[*]
: Panel power VDD is 3.3V by default, 5V or 12V is selectable by jumper
JP7, see section 2.3.5.
[**]
: Grounding of this pin is required to ensure normal LVDS output.
Pin Signal Pin Signal
1 VDD
[*]
2 VDD
[*]
3 VDD
[*]
4 VDD
[*]
5 VDD
[*]
6 VDD
[*]
7 N/C 8 N/C
9 GND 10 GND
11 LVDS_B_DATA3- 12 LVDS_B_DATA0-
13 LVDS_ 14 LVDS_
15 GND 16 GND
17 LVDS_B_CLK- 18 LVDS_B_DATA1-
19 LVDS_B_ CLK + 20 LVDS_
21 GND 22 GND
23 LVDS_A_DATA0- 24 LVDS_B_DATA2-
25 LVDS_ 26 LVDS_
27 GND 28 GND
29 LVDS_A_DATA1- 30 LVDS_A_DATA3-
31 LVDS_ 32 LVDS_
33 LVDS_PRSNT#(Detect)
[**]
34 GND
35 LVDS_A_DATA2- 36 LVDS_A_CLK-
37 LVDS_ 38 LVDS_A_ CLK +
39 GND 40 GND