
BIOS SETUP
32
MI812 User’s Manual
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
By SPD
ITEM HELP
CAS Latency Time
Auto
Menu Level >
DRAM RAS# to CAS# Delay
Auto
DRAM RAS# Precharge
Auto
Precharge delay (tRAS)
Auto
System Memory Frequency
Auto
SLP_S4# Assertion Width
4 to 5 Sec
System BIOS Cacheable
Enabled
Video BIOS Cacheable
Disabled
Memory Hole at 15M-16M
Disabled
PCI Express Root Port Func
Press Enter
** On-Chip VGA Setting **
On-Chip Frame Buffer Size
8MB
DVMT Mode
DVMT
DVMT/FIXED memory Size
128MB
SDVO Device Setting
None
SDVO LVDS Protocol
1 CH SPGW 18bit
SDVO Panel Number
640 x 480
Boot Display
CRT
Panel Scaling
Auto
Panel Number
1024x768 18 bit SC
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is
By SPD
.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The
system board designer should set the values in this field, depending on
the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to
accumulate its charge before the SDRAM refreshes. The default setting
for the Active to Precharge Delay is Auto.
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