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Qorvo 1800MHz Small Cell RF Card Hardware User’s Guide

Hardware User’s Guide

5.7

GPIO Assignments

There  are  40  digital  control  signals  available  through  RFMC  LPAF  connectors  J47  and  J94  on
ZCU111.  They are the 1.8V ADCIO (20 signals on J47) and DACIO (20 signals on J94) lines from
the RFSoC ZU+ device.

The table below shows how the GPIO pins have been assigned. Note that the Zynq firmware pin
number assignments can be found in the Vivado project file

qorvo_spi_slave.xdc

. This file can

be found in the Avnet reference design (see 5.5) inside the pl\qorvo1800\revB\src folder.

Table 1

– Assignments for Digital GPIO from the ZCU111

ZCU111

Signal

Zynq
Pin #

ZCU111

LPAF Pin

Qorvo Card Signal

Qorvo Card

Test Pin

Description

DACIO_00 A9

J94 pin A37 I2C_ SCLX

J5 pin 3

I2C clock for EEPROM

DACIO_01 A10

J94 pin A39 I2C_ SDAX

J5 pin 2

I2C data for EEPROM

DACIO_02 A6

J94 pin B36

CH1_RX_LNA0_BYPX

J1 pin 13

Ch1 Rx LNA0 Bypass

DACIO_03 A7

J94 pin B38

CH1_RX_LNA1_BYPX

J1 pin 14

Ch1 Rx LNA1 Bypass

DACIO_04 A5

J94 pin B40

CH1_RX_LNA0_DISX

J1 pin 15

Ch1 Rx LNA0 Disable

DACIO_05 B5

J94 pin C37

CH1_RX_LNA0_ENX

J1 pin 16

Ch1 Rx LNA0 Enable

DACIO_06 C5

J94 pin C39

CH1_RX_OVX

Ch1 Rx Over-voltage

DACIO_07 C6

J94 pin D36 CH1_TX_PA_ENX

J1 pin 11

Ch1 Tx PA Enable

DACIO_08 B9

J94 pin D38 CH1_RX_LNA1_DISX

J1 pin 17

Ch1 Rx LNA1 Disable

DACIO_09 B10

J94 pin D40 CH1_TX_LNA_DISX

J1 pin 12

Ch1 Tx LNA Disable

DACIO_10 B7

J94 pin E37

CH1_LEX

J1 pin 2

Ch1 Tx and DPD DSA Serial Latch Enable

DACIO_11 B8

J94 pin E39

CH1_CLKX

J1 pin 3

Ch1 Tx and DPD DSA Serial Clock

DACIO_12 D8

J94 pin F36

CH1_SIX

J1 pin 4

Ch1 Tx and DPD DSA Serial Data

DACIO_13 D9

J94 pin F38

CH1_RX_DSA_D0X

J1 pin 5

Ch2 Rx DSA Data bit 0

DACIO_14 C7

J94 pin F40

CH1_RX_DSA_D1X

J1 pin 6

Ch2 Rx DSA Data bit 1

DACIO_15 C8

J94 pin G37 CH1_RX_DSA_D2X

J1 pin 7

Ch2 Rx DSA Data bit 2

DACIO_16 C10

J94 pin G39 CH1_RX_DSA_D3X

J1 pin 8

Ch2 Rx DSA Data bit 3

DACIO_17 D10 J94 pin H36 CH1_RX_DSA_D4X

J1 pin 9

Ch2 Rx DSA Data bit 4

DACIO_18 D6

J94 pin H38 CH1_RX_DSA_D5X

J1 pin 10

Ch2 Rx DSA Data bit 5

DACIO_19 E7

J94 pin H40

TP7

Spare

ADCIO_00 AP5 J47 pin A2

COMMS_LEDX

J6 pin 18

Yellow LED control

ADCIO_01 AP6 J47 pin A4

TP8

Spare

ADCIO_02 AR6 J47 pin B1

CH2_RX_LNA0_BYPX

J6 pin 13

Ch2 Rx LNA0 Bypass

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Содержание Qorvo

Страница 1: ... 2019 Avnet Inc AVNET Reach Further and the AV logo are registered trademarks of Avnet Inc All other brands are the property of their respective owners Qorvo 1800MHz Small Cell RF Card Hardware User s Guide Version 1 3 ...

Страница 2: ...tenuator DSA DevicesControl Interfaces 13 5 4 1 Parallel DSA Control Interface 13 5 4 2 Serial DSA Control Interface 13 5 5 Rebuilding the Reference Design 16 5 6 SPI Controller 17 5 7 GPIO Assignments 18 5 8 EEPROM and I2C Interface 20 5 9 Digital Test Pins 21 5 10 Status LEDs 23 5 11 RFMC Connector Pin Assignments 24 5 12 Pi Pad Attenuators 29 5 13 ADC Input Protection 30 5 13 1 RX side ADC Over...

Страница 3: ...User s Guide Hardware User s Guide 1 Document Control Document Version 1 3 Document Date 11 November 2019 2 Version History Version Date Comment 1 2 24 Oct 2019 Initial Release 1 3 11 Nov 2019 Added detail to Appendix A Alternate Reverse Build Variant ...

Страница 4: ...2 bit ADC s that can operate up to 4GHZ and eight 14 bit DAC s that can operate up to 6 5GHz The Qorvo uses 4 ADC channels and 2 DAC channels in order to support a 2x2 configuration with observation paths for digital pre distortion DPD The Qorvo card part AES LPA QRF1800 G may be purchased stand alone or bundled in the Zynq UltraScale RFSoC Development Kit This document describes the features and ...

Страница 5: ... chain from antenna to digital using tools from MathWorks and industry leading RF components from Qorvo We extend the functionality of the Xilinx Zynq UltraScale RFSoC ZCU111 Evaluation Kit by adding a Qorvo 2x2 Small Cell RF front end 1 8 GHz card for over the air transmission plus native connection to MATLAB Simulink with Avnet s RFSoC Explorer application Figure 2 Using the Avnet RFSoC Explorer...

Страница 6: ...l Communications Commission FDD Frequency Division Duplexing GPIO General Purpose Input Output I2C Inter Integrated Circuit interface IC Industry Canada certification IPMI Intelligent Platform Management Interface LNA Low Noise Amplifier LTE Long Term Evolution 4G telecommunications standard PA Power Amplifier PL Zynq UltraScale RFSoC Programmable Logic PS Zynq UltraScale RFSoC Processing System R...

Страница 7: ... Evaluation Board User Guide 2 AES QRF1800 G Schematic for Qorvo 2x2 Small Cell RF Front end 1 8GHz 3 Xilinx Vivado Design Suite 4 Xilinx Software Development Kit 5 Zynq UltraScale RFSoC RF Data Converter 2 1 LogiCORE IP Product Guide PG269 6 Zynq UltraScale RFSoC Data Sheet DC and AC Switching Characteristics DS926 ...

Страница 8: ... 3 1800 MHz FDD System Alternate tuning options available as BOM variants Transmit signal chain 2x o TQQ0303 1842 5 MHz RF BAW Filter o TQL9092 driver amplifier o RFSA3713 Digital Step Attenuator o QPA9903 0 5 Watt High Efficiency Linearizable Power Amplifier o QPQ1297 Band 3 BAW Duplexer Receive signal chain 2x o QPQ1297 Band 3 BAW Duplexer o TQQ0302 1747 5 MHz RF BAW Filter Band 3 Uplink o TQP4M...

Страница 9: ...Page 9 4 2 Block Diagram Figure 3 Block Diagram ...

Страница 10: ...onnectors on the Qorvo RF card plug into the corresponding LPAF connectors on the ZCU111 These connectors carry the analog I O associated with RFSoC as well as the digital control signals The diagram below illustrates how components inside the ZU28 are connected to the daughter card via these LPAF LPAM connectors Figure 4 Controlling the Qorvo card from the RFSoC Processing System ...

Страница 11: ...not connected to the Qorvo card s RF ground RGND Note that this is not the factory default power configuration and that here external 5V to the Qorvo card requires R140 and R141 to be removed The digital isolators used to achieve separation are the Texas Instruments devices ISO7140 4 channels forward and ISO7141 3 channels forward 1 channel back The Qorvo attenuators use 5V logic The isolators can...

Страница 12: ...R140 which must be removed for any the external power configuration The diagram below shows the default configuration where the Qorvo card is powered from the ZCU111 and R140 and R141 are placed Note that since DGND and RGND are connected much of the isolation is effectively lost In this case 5V is generated by an on board buck converter and LDO Figure 7 Factory Default Configuration with 12V from...

Страница 13: ...rial DSA Control Interface There are not enough GPIO available for a 6 bit interface to all 6 DSA s It is not as important to change the attenuation in the Tx or DPD paths as it is for the receive path Therefore the Tx and DPD attenuators are the Qorvo RFSA3713 https www qorvo com products p RFSA3713 which uses a proprietary serial interface The RFSA3713 can operate from 5MHz to 6GHz It is a 7 bit...

Страница 14: ...Page 14 Qorvo 1800MHz Small Cell RF Card Hardware User s Guide Hardware User s Guide Figure 10 Attenuator Control Interfaces ...

Страница 15: ...nts the serial protocol for these attenuators See 5 5 The image below shows data being clocked out to one of the attenuators on the Channel 1 serial bus The serial clock here is 5MHz The first signal LE is the latch enable signal which toggles after the serial data in SI has been clocked in Figure 11 Scope Capture of SAM signals for Writing to an Attenuator ...

Страница 16: ...ry can be cloned with git clone https github com AvnetDev qorvo1800 git Under Windows the command to clone the tip version of the repository would be git clone git github com AvnetDev qorvo1800 git For Windows it is important that a reasonably recent version of the Git executable is being used From a command prompt the git version command can be used At the time of this document the latest version...

Страница 17: ...rt or ultimately from MathWorks The Avnet reference design see 5 5 software implementation uses the spidev Linux driver The Vivado project instantiates an axi_quad_spi component and the custom qorvo_spi component that maps the interface to the control signals Figure 13 The Qorvo Card SPI Interface in the Vivado Project Most of the signals driven from this interface behave like typical GPIO in that...

Страница 18: ...NA0_DISX J1 pin 15 Ch1 Rx LNA0 Disable DACIO_05 B5 J94 pin C37 CH1_RX_LNA0_ENX J1 pin 16 Ch1 Rx LNA0 Enable DACIO_06 C5 J94 pin C39 CH1_RX_OVX Ch1 Rx Over voltage DACIO_07 C6 J94 pin D36 CH1_TX_PA_ENX J1 pin 11 Ch1 Tx PA Enable DACIO_08 B9 J94 pin D38 CH1_RX_LNA1_DISX J1 pin 17 Ch1 Rx LNA1 Disable DACIO_09 B10 J94 pin D40 CH1_TX_LNA_DISX J1 pin 12 Ch1 Tx LNA Disable DACIO_10 B7 J94 pin E37 CH1_LEX...

Страница 19: ... LNA1 Disable ADCIO_09 AT7 J47 pin D5 CH2_TX_LNA_DISX J6 pin 12 Ch2 Tx LNA Disable ADCIO_10 AU5 J47 pin E2 CH2_LEX J6 pin 2 Ch2 Tx and DPD DSA Serial Latch Enable ADCIO_11 AT5 J47 pin E4 CH2_CLKX J6 pin 3 Ch2 Tx and DPD DSA Serial Clock ADCIO_12 AU3 J47 pin F1 CH2_SIX J6 pin 4 Ch2 Tx and DPD DSA Serial Data ADCIO_13 AU4 J47 pin F3 CH2_RX_DSA_D0X J6 pin 5 Ch2 Rx DSA Data bit 0 ADCIO_14 AV5 J47 pin ...

Страница 20: ...o a specific board s serial number Currently this functionality has not been implemented yet Avnet has Intelligent Platform Management Interface IPMI EEPROMs for identification on some boards Inside the Avnet reference design see 5 5 the RFTOOL codebase includes modules for I2C communication I2C can be accessed from the ZCU111 through the LPAM LPAF connectors During production the EEPROM can also ...

Страница 21: ...ally on one 3 3V pin the second 3 3V pin may be used to jumper between pins 20 and 21 in order to short out the level translator Table 3 Test Header Pin Assignments Pin Signal Description J1 pin 1 DGND Digital Ground J1 pin 2 CH1_LEX Ch1 Tx and DPD DSA Serial Latch Enable J1 pin 3 CH1_CLKX Ch1 Tx and DPD DSA Serial Clock J1 pin 4 CH1_SIX Ch1 Tx and DPD DSA Serial Data J1 pin 5 CH1_RX_DSA_D0X Ch2 R...

Страница 22: ...1 pin 19 UTIL_3V3 3 3V J1 pin 20 UTIL_3V3 3 3V J1 pin 21 VBUS_1V8 1 8V J1 pin 22 DGND Digital Ground J6 pin 1 DGND Digital Ground J6 pin 2 CH2_LEX Ch2 Tx and DPD DSA Serial Latch Enable J6 pin 3 CH2_CLKX Ch2 Tx and DPD DSA Serial Clock J6 pin 4 CH2_SIX Ch2 Tx and DPD DSA Serial Data J6 pin 5 CH2_RX_DSA_D0X Ch2 Rx DSA Data bit 0 J6 pin 6 CH2_RX_DSA_D1X Ch2 Rx DSA Data bit 1 J6 pin 7 CH2_RX_DSA_D2X ...

Страница 23: ...X_LNA1_DISX Ch2 Rx LNA1 Disable J6 pin 18 COMMS_LEDX Yellow LED control J6 pin 19 UTIL_3V3 3 3V J6 pin 20 UTIL_3V3 3 3V J6 pin 21 VBUS_1V8 1 8V J6 pin 22 DGND Digital Ground 5 10 Status LEDs These are the status LED s on the board Table 4 Status LEDs LED Color Description D1 Red Ch1 Rx LNA0 Overload see 5 13 1 D2 Red Ch2 Rx LNA0 Overload see 5 13 1 D3 Yellow Software controlled Comms indicator D4 ...

Страница 24: ...Guide 5 11 RFMC Connector Pin Assignments The two tables below show the ZCU111 LPAF connector pin assignments as per the Xilinx documentation for the board table 3 21 of the ZCU111 Board User Guide 1 Figure 16 RFMC DAC LPAF Connector J94 Vertical Orientation A1 Upper Right Corner ...

Страница 25: ...Page 25 Qorvo 1800MHz Small Cell RF Card Hardware User s Guide Hardware User s Guide Figure 17 RFMC RF ADC LPAF Connector J47 Vertical Orientation A1 in Upper Right Corner ...

Страница 26: ...Chip Pin ZCU111 Signal Name Qorvo Signal Name J4A 1 12V 34 UTIL_3V3 35 VBUS_1V8 37 A9 DACIO_00 I2C_SCLX 39 A10 DACIO_01 I2C_SDAX J4B 1 12V 10 DAC_00_N 19 DAC_06_N 22 NC 34 UTIL_3V3 36 A6 DACIO_02 CH1_RX_LNA0_BYPX 38 A7 DACIO_03 CH1_RX_LNA1_BYPX 40 A5 DACIO_04 CH1_RX_LNA0_DISX J4C 1 12V 10 DAC_00_P 19 DAC_06_P 34 UTIL_3V3 35 VBUS_1V8 37 B5 DACIO_05 CH1_RX_LNA0_ENX 39 C5 DACIO_06 CH1_RX_OVX J4D 1 12...

Страница 27: ... 34 UTIL_3V3 36 D8 DACIO_12 CH1_SIX 38 D9 DACIO_13 CH1_RX_DSA_D0X 40 C7 DACIO_14 CH1_RX_DSA_D1X J4G 34 UTIL_3V3 37 C8 DACIO_15 CH1_RX_DSA_D2X 39 C10 DACIO_16 CH1_RX_DSA_D3X J4H 34 UTIL_3V3 36 D10 DACIO_17 CH1_RX_DSA_D4X 38 D6 DACIO_18 CH1_RX_DSA_D5X 40 E7 DACIO_19 TP7 Table 6 Channel 2 RFMC J7 mates with ZCU111 J47 Conn Pin ZCU111 Chip Pin ZCU111 Signal Name Qorvo Signal Name J7A 2 AP5 ADCIO_00 CO...

Страница 28: ...C_01_N 13 ADC_03_N 16 ADC_05_N 19 ADC_07_N J7C 2 AU7 ADCIO_05 CH2_RX_LNA0_ENX 4 AV8 ADCIO_06 CH2_RX_OVX 6 VBUS_1V8 7 UTIL_3V3 10 ADC_01_P 13 ADC_03_P 16 ADC_05_P 19 ADC_07_P J7D 1 AU8 ADCIO_07 CH2_TX_PA_ENX 3 AT6 ADCIO_08 CH2_RX_LNA1_DISX 5 AT7 ADCIO_09 CH2_TX_LNA_DISX 7 UTIL_3V3 J7E 2 AU5 ADCIO_10 CH2_LEX 4 AT5 ADCIO_11 CH2_CLKX 7 UTIL_3V3 J7F 1 AU3 ADCIO_12 CH2_SIX 3 AU4 ADCIO_13 CH2_RX_DSA_D0X ...

Страница 29: ...7 CH2_RX_DSA_D4X 3 AV2 ADCIO_18 CH2_RX_DSA_D5X 5 AV3 ADCIO_19 TP9 7 UTIL_3V3 5 12 Pi Pad Attenuators There are 2 dB balanced Pi pad attenuators on the Qorvo card PCB between the RFSoC ADC DAC connections within the SAMTEC LPAF connector and the baluns on the Qorvo card Resistor values are shown below Also note the 100 nF AC coupling capacitors Target performance better than 10 dB return loss up to...

Страница 30: ...g op amp with make up gain of 4 to compensate for the attenuation of the resistive coupling followed by an open loop op amp comparator whose voltage threshold is set to trigger at 1 2 V which corresponds to the maximum input level of 1V pk pk at the RFSoC ADC input pins Under this condition the LNA immediately switches to the LNA OFF Bypass OFF state whereby the RFSoC ADC input will reduce to sign...

Страница 31: ...hrough LPAF M and the comparator and AD8361 power detector These signals are also routed to the Digital Test Pins for scenarios where the Qorvo card may be used in standalone mode within a test harness independent of the ZCU111 Figure 20 Rx Side LNA Control The relation between the LNA0 Enable Disable one Over Voltage signals is illustrated in this table from sheet 6 of the schematic 2 Figure 21 T...

Страница 32: ...mall amounts of back power 5 15 Circulator After the Directional Coupler the Ch1 DPD signal passes through U16 the Circular Isolator Circulator It ensures any reflected signal due to impedance mismatch at U17 is circulated to ground instead of coming back towards the transmitter The RF circulator is behind the duplexer to maximize the Noise Figure of the receiver chain In other words putting the c...

Страница 33: ...ate such items in a finished product and 2 Software developers to write software applications for use with the end product This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained Operation is subject to the condition that this product not cause harmful interference to licensed radio stations a...

Страница 34: ...avenues to search depending on your needs For documentation technical specifications and videos visit the Avnet RFSoC kit page www avnet com rfsockit If you have questions please use the RFSoC Kit forum on our Element 14 ZedBoard Community page https www element14 com zedboardcommunity ...

Страница 35: ...onvenient functional testing and demos of the card without external test equipment the layout was made with Reverse Variant provision to enable swapping uplink and downlink paths to perform a loopback test Reverse Variant Component Modifications Configuring the card as a Reverse Variant requires the following component modifications 2 1 Enable CH2 downlink at 1747 5 MHz by replacing bandpass filte...

Страница 36: ...gnal Conditioning Band3 Dnlnk BW 75MHz LowDrift BAW QORVO TQQ0303 U33 Isolator 1805 1880MHz 20W RFMW RFSL5504 U33 Isolator 1710 1785MHz 20W RFMW RFSL5408 C204 C205 CAP CER 100PF 50V C0G NP0 0603 KEMET C0603C101K5GACTU C206 C207 CAP CER 100PF 50V C0G NP0 1206 KEMET C1206C101J5GACTU Cap swap info RF Transmit Channel 1 caps are identical across variants RF Transmit Channel 2 requires the capacitor sw...

Страница 37: ... configure the card but requires modification to the board which will void the standard warranty for the Qorvo card Only attempt these changes if you have adequate board rework equipment and expertise For the REVERSE configuration C206 can be re soldered to location of C207 Likewise C204 can be re soldered to location of C205 Figure 26 Channel 2 capacitor position for NORMAL configuration top laye...

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