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22 Sept 2016
v1.1
2 Functional Description
The PZCC-FMC-V2 Carrier is an expansion board for the PicoZed SOMs. The primary I/O
interface is via the LPC FMC connector. The board features additional MGT lanes for PCIe and
SFP+. The PZCC-FMC-V2 bridges Avnet’s PicoZed SOM products to common high speed
interfaces.
In addition to the LPC FMC connector, the PZCC-FMC-V2 also has 4 Digilent Pmod™ compatible
interfaces, a SFP+ connector, a Micro SD card, Dual function JTAG port (FMC & SOM), an HDMI
port, 2 USB ports (UART and OTG TYPE A 2.0), PCIe x1 Gen 2.0 edge connector and a SOM
driven Ethernet port.
The board includes user adjustable operational features to aid in product design and
development. Such features include software configurable MGT clock synthesizer SMA MGT
(TX/RX) data inputs and a user adjustable VADJ power plane.
The board’s HDMIO I2C bus, nets labeled: HDMIO_SCL/SDA is the board’s primary I2C bus and
can be considered the “board I2C bus”. More information can be found in section:
2.1 Reset sources
System Power Reset: PG_MODULE_N - SW9
The PG_MODULE signal is an active high 2.75V signal. When high, it indicates both the carrier
and SOM power supplies are within their regulation tolerance parameters and functional. The
signal is held low until the power supplies have completed their successful sequencing routine.
Green LED D4 illuminates when this signal is high.
The user can force this pin low by depressing SW9, which will trigger a reboot of the Zynq
device. Depressing this button will not cause a hard power cycle, however the PS and PL on
the Zynq device will be reset to power on default settings and the selected boot process is
initiated based on the boot configuration setting of the SOM.
SOM
Net Name:
Carrier Net Name:
JX2 Pin #:
PG_MODULE
PG_MODULE
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Table 2 – PG_MODULE Connection
Processor Subsystem Reset: CARRIER_SRST_N - SW8
The SYS_RST# button provides an active low signal to net CARRIER_SRST_N which allows
the user to reset all of the PL logic on the SOM FPGA without disturbing the debug
environment. For example, the previous breakpoints set by the user remain valid after system
reset. Due to security concerns, system reset erases all memory content within the PS,
including the OCM. The PL is also reset in system reset. Upon de-assertion of this signal, the
SoC does not re-sample the boot mode strapping pins.
SOM
Net Name:
Carrier Net Name:
JX1 Pin #:
CARRIER_SRST_N
CARRIER_SRST_N
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Table 3 – CARRIER_SRST_N Connection
